公开(公告)号：US20230207412A1

公开(公告)日：2023-06-29

申请号：US17561432

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Ronald SPREITZER ,  Jason GARCIA ,  Ankur AGRAWAL ,  Eleanor Patricia Paras RABADAM ,  Guiyun BAI

IPC: H01L23/31 ,  H01L23/00 ,  B81C1/00 ,  H01L21/48 ,  H01L21/56 ,  B81B7/00 ,  H01S5/0234 ,  H01S5/50

CPC classification number: H01L23/3157 ,  H01L24/16 ,  B81C1/00301 ,  H01L21/4853 ,  H01L21/563 ,  B81B7/007 ,  H01S5/0234 ,  H01S5/50 ,  B81B2207/07 ,  H01L2924/146 ,  H01L2224/16227 ,  H01L2924/1461 ,  H01L2924/18161

Abstract: Example techniques to enable a flip chip underfill exclusion zone include use of bump barriers, films or etched substrate cavities to prevent underfill from reaching the flip chip underfill exclusion zone.

公开(公告)号：US20230093438A1

公开(公告)日：2023-03-23

申请号：US17481266

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Benjamin DUONG ,  Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Darko GRUJICIC ,  Bai NIE ,  Tarek A. IBRAHIM ,  Ankur AGRAWAL ,  Sandeep GAAN ,  Ravindranath V. MAHAJAN ,  Aleksandar ALEKSOV

IPC: G02B6/12 ,  H04B10/70 ,  G02B6/124 ,  G02B6/13

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a first layer, where the first layer comprises glass. In an embodiment, a second layer is over the first layer, where the second layer comprises a mold material. In an embodiment, a first photonics integrated circuit (PIC) is within the second layer. In an embodiment, a second PIC is within the second layer, and a waveguide is in the first layer. In an embodiment, the waveguide optically couples the first PIC to the second PIC.

公开(公告)号：US20220416503A1

公开(公告)日：2022-12-29

申请号：US17357938

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Priyanka DOBRIYAL ,  Aditi MALLIK ,  Saeed FATHOLOLOUMI ,  Ankur AGRAWAL ,  Anna PRAKASH ,  Hemant Mahesh SHAH ,  Raiyomand ASPANDIAR ,  Neil Raymund CARANTO

IPC: H01S5/024 ,  H01S5/34

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to thermal routing techniques within a hybrid silicon laser or photonics integrated circuit to facilitate heat extraction during laser operation. In particular dual metal layers, with a top metal layer thermally coupled with P node above a quantum well and extending substantially under a heat sink, and a bottom metal layer thermally coupled with an N node, where the top metal layer and the bottom metal layer are not electrically coupled. Other embodiments may be described and/or claimed.

公开(公告)号：US20210074866A1

公开(公告)日：2021-03-11

申请号：US16562889

申请日：2019-09-06

Applicant: Intel Corporation

Inventor： Priyanka DOBRIYAL ,  Ankur AGRAWAL ,  Susheel JADHAV ,  Quan TRAN ,  Raghuram NARAYAN ,  Raiyomand ASPANDIAR ,  Kenneth BROWN ,  John HECK

IPC: H01L31/0232 ,  G02B3/00 ,  H01L31/0216 ,  H01L31/02 ,  H01L25/16 ,  H01L23/538 ,  H01L31/18 ,  G02B1/11 ,  G02B6/42

Abstract: Embodiments disclosed herein include optoelectronic systems and methods of forming such systems. In an embodiment the optoelectronic system comprises a board, and a carrier attached to the board. In an embodiment, a first die is on the carrier. In an embodiment, the first die is a photonics die, and a surface of the first die is covered by an optically transparent layer.

公开(公告)号：US20230318247A1

公开(公告)日：2023-10-05

申请号：US17710881

申请日：2022-03-31

Applicant: INTEL cORPORATION

Inventor： Eleanor Patricia Paras RABADAM ,  Guiyun BAI ,  Sanjeev GUPTA ,  Ronald SPREITZER ,  Jonathan DOYLEND ,  Ankur AGRAWAL ,  Boping XIE ,  Sushrutha Reddy GUJJULA ,  Jason GARCIA ,  Kenneth BROWN ,  Dan WANG ,  Daniel GRODENSKY ,  Israel PETRONIUS ,  Konstantin MATYUCH

IPC: H01S3/04

CPC classification number: H01S3/0405

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a package that includes multiple PICs in the package that are optically coupled with each other. In embodiments, the package may include discrete electronic and optical components, and thermal management solutions for co-packaging of multiple PICs. Other embodiments may be described and/or claimed.

公开(公告)号：US20210210478A1

公开(公告)日：2021-07-08

申请号：US17191615

申请日：2021-03-03

Applicant: Intel Corporation

Inventor： Susheel JADHAV ,  Juan DOMINGUEZ ,  Ankur AGRAWAL ,  Kenneth BROWN ,  Yi LI ,  Jing CHEN ,  Aditi MALLIK ,  Xiaoyu HONG ,  Thomas LILJEBERG ,  Andrew C. ALDUINO ,  Ling LIAO ,  David HUI ,  Ren-Kang CHIOU ,  Harinadh POTLURI ,  Hari MAHALINGAM ,  Lobna KAMYAB ,  Sasanka KANUPARTHI ,  Sushrutha Reddy GUJJULA ,  Saeed FATHOLOLOUMI ,  Priyanka DOBRIYAL ,  Boping XIE ,  Abiola AWUJOOLA ,  Vladimir TAMARKIN ,  Keith MEASE ,  Stephen KEELE ,  David SCHWEITZER ,  Brent ROTHERMEL ,  Ning TANG ,  Suresh POTHUKUCHI ,  Srikant NEKKANTY ,  Zhichao ZHANG ,  Kaiyuan ZENG ,  Baikuan WANG ,  Donald TRAN ,  Ravindranath MAHAJAN ,  Baris BICEN ,  Grant SMITH

IPC: H01L25/18 ,  H01L23/473 ,  H01R12/71

Abstract: Embodiments disclosed herein include electronic packages for optical to electrical switching. In an embodiment, an electronic package comprises a first package substrate and a second package substrate attached to the first package substrate. In an embodiment, a die is attached to the second package substrate. In an embodiment, a plurality of photonic engines are attached to a first surface and a second surface of the first package substrate. In an embodiment, the plurality of photonic engines are communicatively coupled to the die through the first package substrate and the second package substrate.