公开(公告)号：US12255147B2

公开(公告)日：2025-03-18

申请号：US17243784

申请日：2021-04-29

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon Marin ,  Srinivas Pietambaram ,  Suddhasattwa Nad

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: An electronic substrate may be fabricated having at least two glass layers separated by an etch stop layer, wherein a bridge is embedded within one of the glass layers. The depth of a cavity formed for embedding the bridge is control by the thickness of the glass layer rather than by controlling the etching process used to form the cavity, which allows for greater precision in the fabrication of the electronic substrate. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate, such that the bridge provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board.

公开(公告)号：US20240222320A1

公开(公告)日：2024-07-04

申请号：US18091265

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Gang Duan ,  Srinivas Pietambaram ,  Brandon Marin ,  Jeremy Ecton

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/5381 ,  H01L23/5383 ,  H01L24/08 ,  H01L25/50 ,  H01L2224/08145

Abstract: Multi-chip/die device including two or more substantially coplanar base IC dies directly bonded to a bridge IC die over or under the base IC dies. Direct bonding of the bridge IC die provides high pitch interconnect. A package metallization routing structure including conductive vias adjacent to the bridge IC die may be built up and terminate at first level interconnect interfaces. A temporary carrier, such as glass, may be employed to form such multi-chip devices.

公开(公告)号：US20240113005A1

公开(公告)日：2024-04-04

申请号：US17957751

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Aleksandar Aleksov ,  Hiroki Tanaka ,  Brandon Marin ,  Srinivas Pietambaram ,  Xavier Brun

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13

CPC classification number: H01L23/49833 ,  H01L21/4803 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/16 ,  H01L2224/0346 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/16146 ,  H01L2224/1624 ,  H01L2224/80201 ,  H01L2224/80379 ,  H01L2924/0665

Abstract: Microelectronic integrated circuit package structures include a first substrate coupled to a second substrate by a conductive interconnect structure and a dielectric material adjacent to the conductive interconnect structure. A cavity in a surface of the first substrate is adjacent to the conductive interconnect structure. A portion of the dielectric material is within the cavity.

公开(公告)号：US20250022908A1

公开(公告)日：2025-01-16

申请号：US18221601

申请日：2023-07-13

Applicant: Intel Corporation

Inventor： Brandon Marin ,  Khaled Ahmed ,  Srinivas Pietambaram ,  Gang Duan

IPC: H01L27/15

Abstract: Techniques and mechanisms for a micro-LED (or “uLED”) device to facilitate communication of an optical signal which is propagated via a transparent substrate structure. In an embodiment, one or more recess structures are formed in a side of a transparent substrate structure, such as a glass core of a package substrate. A uLED structure extends partially through the transparent substrate structure in a first recess structure, and is oriented to transmit or receive an optical signal via the transparent substrate. In another embodiment, the uLED structure is coupled to integrated circuitry which provides functionality to operate the uLED structure, at different times, in either one of an optical signal receiver mode or an optical signal transmitter mode.

公开(公告)号：US20240219633A1

公开(公告)日：2024-07-04

申请号：US18090258

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Brandon Marin ,  Jeremy Ecton ,  Gang Duan ,  Srinivas Pietambaram

IPC: G02B6/122 ,  G02B6/138

CPC classification number: G02B6/1221 ,  G02B6/138 ,  G02B2006/12038

Abstract: An integrated circuit (IC) module includes a photonic IC, an electrical IC, and a switchable waveguide device that, using a signal from the electrical IC, controls optical signals to or from the photonic IC. The switchable waveguide device may be formed by coupling metallization structures on both sides of, and either level with or below, a nonlinear optical material. The metallization structures may be in the photonic or electrical IC. The nonlinear optical material may be above the electrical IC in the photonic IC or on a glass substrate. The photonic and electrical ICs may be hybrid bonded or soldered together. The IC module may be coupled to a system substrate.

公开(公告)号：US20240213235A1

公开(公告)日：2024-06-27

申请号：US18089459

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Srinivas Pietambaram ,  Brandon Marin ,  Jeremy Ecton ,  Gang Duan

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/1427 ,  H01L2924/1431

Abstract: An apparatus is provided which comprises: an integrated circuit logic device, an integrated circuit power device conductively coupled with a first surface of the integrated circuit logic device, wherein the integrated circuit power device extends laterally beyond a side of the integrated circuit logic device, one or more vias adjacent the side of the integrated circuit logic device extending from contact with the integrated circuit power device to level with a second surface of the integrated circuit logic device opposite the first surface of the integrated circuit logic device, and conductive contacts on the second surface of the integrated circuit logic device. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240113029A1

公开(公告)日：2024-04-04

申请号：US17957783

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon Marin ,  Srinivas Pietambaram ,  Hiroki Tanaka ,  Suddhasattwa Nad

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/13 ,  H01L23/15 ,  H01L25/16

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L23/13 ,  H01L23/15 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/16 ,  H01L24/16

Abstract: Multi-die packages including at least one glass substrate within a space between two adjacent IC dies or surrounding an interconnect bridge die. The various IC dies may be placed within recesses formed in the glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. The bridge die may be directly bonded or soldered to the adjacent IC dies, providing fine pitch interconnect. The opposite side of the adjacent IC dies and glass substrate may be attached to a host component or may be built up with package dielectric material. Metallization features formed on the second side of the glass substrate may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects.

公开(公告)号：US20240038735A1

公开(公告)日：2024-02-01

申请号：US18225044

申请日：2023-07-21

Applicant: Intel Corporation

Inventor： Khaled Ahmed ,  Brandon Marin

IPC: H01L25/075 ,  H01L33/24 ,  H01L33/50

CPC classification number: H01L25/0753 ,  H01L33/24 ,  H01L33/502

Abstract: Techniques and mechanisms for a micro-LED (“uLED”) structure to facilitate efficient communication of an optical signal. In an embodiment, a columnar “nanopost” uLED structure comprises contiguous bodies of respective semiconductor materials, including a first body of a doped semiconductor material. The first body forms a pyramidal structure, wherein one or more others of the contiguous bodies are arranged on the first body in a vertically stacked configuration. More particularly, a second body of an undoped semiconductor material is to provide a quantum well of the uLED structure, wherein the second body does not cover or otherwise extend along vertical sidewall structures of the first body. In another embodiment, the pyramidal structure, in combination with the vertically stacked arrangement of semiconductor bodies, facilitates efficient communication of narrowly columnated optical signal by mitigating optical signal communication via vertical sides of the uLED structure.

公开(公告)号：US20220399150A1

公开(公告)日：2022-12-15

申请号：US17348580

申请日：2021-06-15

Applicant: Intel Corporation

Inventor： Brandon Marin ,  Jeremy Ecton ,  Suddhasattwa Nad ,  Matthew Tingey ,  Ravindranath Mahajan ,  Srinivas Pietambaram

IPC: H01F27/28 ,  H01L25/18 ,  H01L23/498 ,  H01F27/32

Abstract: An electronic substrate may be fabricated having a dielectric material, metal pads embedded in the dielectric material with co-planar surfaces spaced less than one tenth millimeter from each other, and a metal trace embedded in the dielectric material and attached between the metal pads, wherein a surface of the metal trace is non-co-planar with the co-planar surfaces of the metal pads at a height of less than one millimeter, and wherein sides of the metal trace are angled relative to the co-planar surfaces of the metal pads. In an embodiment of the present description, an embedded angled inductor may be formed that includes the metal trace. In an embodiment, an integrated circuit package may be formed with the electronic substrate, wherein at least one integrated circuit devices may be attached to the electronic substrate. Other embodiments are disclosed and claimed.

公开(公告)号：US20210296225A1

公开(公告)日：2021-09-23

申请号：US16827085

申请日：2020-03-23

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Ravindranath Mahajan ,  Brandon Marin ,  Jeremy Ecton ,  Mohammad Mamunar Rahman

IPC: H01L23/50 ,  H01L29/06

Abstract: An integrated circuit package comprising an integral structural member embedded within dielectric material and at least partially surrounding a keep-out zone of a co-planar package metallization layer. The integral structural member may increase stiffness of the package without increasing the package z-height. The structural member may comprise a plurality of intersecting elements. Individual structural elements may comprise conductive vias that are non-orthogonal to a plane of the package. An angle of intersection and thickness of the structural elements may be varied to impart more or less local or global rigidity to a package according to a particular package application. Intersecting openings may be patterned in a mask material by exposing a photosensitive material through a half-penta prism. Structural material may be plated or otherwise deposited into the intersecting openings.