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    Apparatus and method to increase effective capacitance with layout staples
    1.
    发明授权
    Apparatus and method to increase effective capacitance with layout staples 有权

    公开(公告)号：US12230569B2

    公开(公告)日：2025-02-18

    申请号：US17177055

    申请日：2021-02-16

    Applicant: Intel Corporation

    Inventor： Kushal Sreedhar ,  Christopher Mozak ,  Mahmoud Elassal

    IPC: H01L23/528 ,  H01L23/522 ,  G11C5/14 ,  G11C11/16

    Abstract: A scheme intelligently balances existing TM0 resources to simultaneously boost both AC and DC power delivery topologies without incurring a penalty on either area or IR drop. TM0 tracks are either regular or staples. Regular tracks are continuous across the width of an active silicon. Staples are located right under the respective TM1 (Top Metal 1) tracks. TM1 is above TM0 in the hierarchy of metal layers. The staples aid in increasing the total TV0 (Top Via 0 that connects TM0 to TM1) density for all supplies simultaneously as they are consecutively track-shared between the TM1 tracks. This boost in via density helps reduce the net series resistance of the MIM capacitor as the Manhattan (displacement) distance between the supply and ground vias is now reduced. The outcome is a high-density high-bandwidth MIM capacitor, located between the main power distribution layers in the die metal stack—TM0 and TM1.

    Dynamic reconfigurable dual power I/O receiver
    3.
    发明授权
    Dynamic reconfigurable dual power I/O receiver 审中-公开

    公开(公告)号：US10672438B2

    公开(公告)日：2020-06-02

    申请号：US16147635

    申请日：2018-09-29

    Applicant: Intel Corporation

    Inventor： Mohammed G. Mostofa ,  Roger K. Cheng ,  Aaron Martin ,  Christopher Mozak ,  Pavan Kumar Kappagantula ,  Hsien-Pao Yang

    IPC: G11C7/10 ,  G06F1/3234 ,  G06F13/16

    Abstract: An apparatus is provided which comprises: a first circuitry to sample a first input signal to generate a first sampled signal, and to sample a second input signal to generate a second sampled signal, wherein the first input signal comprises data; a second circuitry to receive the first sampled signal and the second sampled signal, and to generate a first pair of differential signals; an offset cancellation circuitry to cancel or reduce an offset in the first pair of differential signals; and a latch to receive the first pair of differential signals subsequent to the cancellation or reduction of the offset, and to output a second pair of differential signals, wherein the second pair of differential signals is indicative of the data.

    Device, method and system for providing a delayed clock signal to a circuit for latching data
    4.
    发明授权
    Device, method and system for providing a delayed clock signal to a circuit for latching data 有权

    公开(公告)号：US10573272B2

    公开(公告)日：2020-02-25

    申请号：US16022357

    申请日：2018-06-28

    Applicant: Intel Corporation

    Inventor： Christopher Mozak ,  Senthil Kumar Sampath

    IPC: H03L7/06 ,  G09G5/00 ,  H03K5/135 ,  H03K5/14 ,  H03L1/00 ,  H03L1/02 ,  H03L7/081 ,  H03K5/00

    Abstract: Techniques and mechanisms for determining a delay to be applied to a clock signal for synchronizing data communication. In an embodiment, a delay is applied to a first clock signal to generate a second clock signal, which is then communicated to a latch circuit via a clock signal distribution path. The delay is determined based on an evaluation of a first time needed for signal communication via a model of the clock signal distribution path. Such determining is further based on an evaluation of a second time for one cycle of a cyclical signal, where said cycle correspond to that of the first clock signal. In another embodiment, multiple different delays are applied each to a different respective clock signal, where each of said delays is based on both the evaluation of the first time and the evaluation of the second time.

    APPARATUS AND METHOD TO INCREASE EFFECTIVE CAPACITANCE WITH LAYOUT STAPLES
    6.
    发明申请
    APPARATUS AND METHOD TO INCREASE EFFECTIVE CAPACITANCE WITH LAYOUT STAPLES 有权

    公开(公告)号：US20210167014A1

    公开(公告)日：2021-06-03

    申请号：US17177055

    申请日：2021-02-16

    Applicant: Intel Corporation

    Inventor： Kushal Sreedhar ,  Christopher Mozak ,  Mahmoud Elassal

    IPC: H01L23/528 ,  H01L23/522

    Abstract: A scheme intelligently balances existing TM0 resources to simultaneously boost both AC and DC power delivery topologies without incurring a penalty on either area or IR drop. TM0 tracks are either regular or staples. Regular tracks are continuous across the width of an active silicon. Staples are located right under the respective TM1 (Top Metal 1) tracks. TM1 is above TM0 in the hierarchy of metal layers. The staples aid in increasing the total TV0 (Top Via 0 that connects TM0 to TM1) density for all supplies simultaneously as they are consecutively track-shared between the TM1 tracks. This boost in via density helps reduce the net series resistance of the MIM capacitor as the Manhattan (displacement) distance between the supply and ground vias is now reduced. The outcome is a high-density high-bandwidth MIM capacitor, located between the main power distribution layers in the die metal stack—TM0 and TM1.

    DYNAMIC RECONFIGURABLE DUAL POWER I/O RECEIVER
    8.
    发明申请
    DYNAMIC RECONFIGURABLE DUAL POWER I/O RECEIVER 审中-公开

    公开(公告)号：US20200105319A1

    公开(公告)日：2020-04-02

    申请号：US16147635

    申请日：2018-09-29

    Applicant: Intel Corporation

    Inventor： Mohammed G. Mostofa ,  Roger K. Cheng ,  Aaron Martin ,  Christopher Mozak ,  Pavan Kumar Kappagantula ,  Hsien-Pao Yang

    IPC: G11C7/10 ,  G06F13/16 ,  G06F1/32

    Abstract: An apparatus is provided which comprises: a first circuitry to sample a first input signal to generate a first sampled signal, and to sample a second input signal to generate a second sampled signal, wherein the first input signal comprises data; a second circuitry to receive the first sampled signal and the second sampled signal, and to generate a first pair of differential signals; an offset cancellation circuitry to cancel or reduce an offset in the first pair of differential signals; and a latch to receive the first pair of differential signals subsequent to the cancellation or reduction of the offset, and to output a second pair of differential signals, wherein the second pair of differential signals is indicative of the data.

    DEVICE, METHOD AND SYSTEM FOR PROVIDING A DELAYED CLOCK SIGNAL TO A CIRCUIT FOR LATCHING DATA
    9.
    发明申请
    DEVICE, METHOD AND SYSTEM FOR PROVIDING A DELAYED CLOCK SIGNAL TO A CIRCUIT FOR LATCHING DATA 审中-公开

    公开(公告)号：US20200005729A1

    公开(公告)日：2020-01-02

    申请号：US16022357

    申请日：2018-06-28

    Applicant: Intel Corporation

    Inventor： Christopher Mozak ,  Senthil Kumar Sampath

    IPC: G09G5/00 ,  H03K5/135 ,  H03K5/14 ,  H03L1/00 ,  H03L7/081 ,  H03L1/02

    Abstract: Techniques and mechanisms for determining a delay to be applied to a clock signal for synchronizing data communication. In an embodiment, a delay is applied to a first clock signal to generate a second clock signal, which is then communicated to a latch circuit via a clock signal distribution path. The delay is determined based on an evaluation of a first time needed for signal communication via a model of the clock signal distribution path. Such determining is further based on an evaluation of a second time for one cycle of a cyclical signal, where said cycle correspond to that of the first clock signal. In another embodiment, multiple different delays are applied each to a different respective clock signal, where each of said delays is based on both the evaluation of the first time and the evaluation of the second time.

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