公开(公告)号：US20230207479A1

公开(公告)日：2023-06-29

申请号：US17561547

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Omkar KARHADE ,  Nitin A. DESHPANDE

IPC: H01L23/544 ,  H01L23/00

CPC classification number: H01L23/544 ,  H01L24/08 ,  H01L23/49816

Abstract: Embodiments disclosed herein include semiconductor devices. In one embodiment, a die comprises a substrate, where the substrate comprises a semiconductor material. In an embodiment, a backend layer is over the substrate, where the backend layer comprises conductive routing. In an embodiment, the die further comprises a protrusion extending out from an edge of the substrate and the backend layer. In an embodiment, a fiducial is on a surface of the protrusion.

公开(公告)号：US20230369071A1

公开(公告)日：2023-11-16

申请号：US18226129

申请日：2023-07-25

Applicant: Intel Corporation

Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Bassam M. ZIADEH ,  Yoshihiro TOMITA

IPC: H01L21/56 ,  H01L23/16 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L21/563 ,  H01L23/16 ,  H01L23/562 ,  H01L25/0657 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/81192 ,  H01L2224/92125 ,  H01L2224/48465 ,  H01L2225/06541 ,  H01L2224/13082 ,  H01L2224/73204 ,  H01L2924/1579 ,  H01L2924/3511 ,  H01L2224/81007 ,  H01L2224/14181 ,  H01L2224/0401 ,  H01L2224/97 ,  H01L2224/81191 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16225 ,  H01L2225/06568 ,  H01L2224/32225 ,  H01L2224/83192 ,  H01L24/32 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2225/06513 ,  H01L24/13 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/81203 ,  H01L2224/81211 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2224/81011 ,  H01L24/81 ,  H01L2924/2064 ,  H01L24/83 ,  H01L2224/26175 ,  H01L24/14 ,  H01L24/73 ,  H01L24/16 ,  H01L2924/1434 ,  H01L2225/06517 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/15311

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

公开(公告)号：US20190148268A1

公开(公告)日：2019-05-16

申请号：US16228378

申请日：2018-12-20

Applicant: Intel Corporation

Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE ,  Rajendra C. DIAS ,  Edvin CETEGEN ,  Lars D. SKOGLUND

IPC: H01L23/485 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L25/065

Abstract: Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.

公开(公告)号：US20230197520A1

公开(公告)日：2023-06-22

申请号：US17557579

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Yi SHI ,  Omkar KARHADE ,  Shawna M. LIFF ,  Zhihua ZOU ,  Ryan MACKIEWICZ ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Arnab SARKAR

IPC: H01L21/822 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/822 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/97 ,  H01L2224/97 ,  H01L2924/15311

Abstract: Embodiments herein relate to systems, apparatuses, or processes for attaching dummy dies to a wafer that includes a plurality of active dies, where the dummy dies are placed along or in dicing streets where the wafer is to be cut during singulation. In embodiments, the dummy dies may be attached to the wafer using a die attach film, or may be attached using hybrid bonding. Other embodiments may be described and/or claimed.

公开(公告)号：US20200350181A1

公开(公告)日：2020-11-05

申请号：US16915290

申请日：2020-06-29

Applicant: Intel Corporation

Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Bassam M. ZIADEH ,  Yoshihiro TOMITA

IPC: H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L23/16

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

公开(公告)号：US20190341271A1

公开(公告)日：2019-11-07

申请号：US16515981

申请日：2019-07-18

Applicant: Intel Corporation

Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Bassam M. ZIADEH ,  Yoshihiro TOMITA

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/16 ,  H01L25/18

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

公开(公告)号：US20250096009A1

公开(公告)日：2025-03-20

申请号：US18961031

申请日：2024-11-26

Applicant: Intel Corporation

Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Bassam M. ZIADEH ,  Yoshihiro TOMITA

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/16 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

公开(公告)号：US20230207522A1

公开(公告)日：2023-06-29

申请号：US17561720

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Omkar KARHADE ,  Nitin A. DESHPANDE ,  Ravindranath V. MAHAJAN

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/538 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L21/568 ,  H01L21/561 ,  H01L23/5389 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105

Abstract: Embodiments disclosed herein include die modules and methods of making die modules. In an embodiment, a die module comprises a first die with a set of first pads with surfaces that are substantially coplanar with a surface of a first dielectric layer. In an embodiment, the die module further comprises a second die with a set of second pads with surfaces that are substantially coplanar with a surface of a second dielectric layer. In an embodiment the first pads are bonded to the second pads and the first dielectric layer is bonded to the second dielectric layer.

公开(公告)号：US20220230892A1

公开(公告)日：2022-07-21

申请号：US17715923

申请日：2022-04-07

Applicant: Intel Corporation

Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Bassam M. ZIADEH ,  Yoshihiro TOMITA

IPC: H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L23/16

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.