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    INCREASED TRANSISTOR SOURCE/DRAIN CONTACT AREA USING SACRIFICIAL SOURCE/DRAIN LAYER
    1.
    发明申请
    INCREASED TRANSISTOR SOURCE/DRAIN CONTACT AREA USING SACRIFICIAL SOURCE/DRAIN LAYER 审中-公开

    公开(公告)号：US20200006525A1

    公开(公告)日：2020-01-02

    申请号：US16023024

    申请日：2018-06-29

    Applicant: INTEL CORPORATION

    Inventor： DAX M. CRUM ,  BISWAJEET GUHA ,  WILLIAM HSU ,  STEPHEN M. CEA ,  TAHIR GHANI

    IPC: H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/02

    Abstract: Integrated circuit structures including increased transistor source/drain (S/D) contact area using a sacrificial S/D layer are provided herein. The sacrificial layer, which includes different material from the S/D material, is deposited into the S/D trenches prior to the epitaxial growth of that S/D material, such that the sacrificial layer acts as a space-holder below the S/D material. During S/D contact processing, the sacrificial layer can be selectively etched relative to the S/D material to at least partially remove it, leaving space below the S/D material for the contact metal to fill. In some cases, the contact metal is also between portions of the S/D material. In some cases, the contact metal wraps around the epi S/D, such as when dielectric wall structures on either side of the S/D region are employed. By increasing the S/D contact area, the contact resistance is reduced, thereby improving the performance of the transistor device.

    ISOLATION SCHEMES FOR GATE-ALL-AROUND TRANSISTOR DEVICES
    2.
    发明申请
    ISOLATION SCHEMES FOR GATE-ALL-AROUND TRANSISTOR DEVICES 审中-公开

    公开(公告)号：US20200006559A1

    公开(公告)日：2020-01-02

    申请号：US16024046

    申请日：2018-06-29

    Applicant: INTEL CORPORATION

    Inventor： RISHABH MEHANDRU ,  STEPHEN M. CEA ,  BISWAJEET GUHA ,  TAHIR GHANI ,  WILLIAM HSU

    IPC: H01L29/78 ,  H01L21/762 ,  H01L21/761 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

    Abstract: Isolation schemes for gate-all-around (GAA) transistor devices are provided herein. In some cases, the isolation schemes include changing the semiconductor nanowires/nanoribbons in a targeted channel region between active or functional transistor devices to electrically isolate those active devices. The targeted channel region is referred to herein as a dummy channel region, as it is not used as an actual channel region for an active or functional transistor device. The semiconductor nanowires/nanoribbons in the dummy channel region can be changed by converting them to an electrical insulator and/or by adding dopant that is opposite in type relative to surrounding source/drain material (to create a p-n junction). The isolation schemes described herein enable neighboring active devices to retain strain in the nanowires/nanoribbons of their channel regions, thereby improving device performance.

    TECHNIQUES FOR FORMING DUAL-STRAIN FINS FOR CO-INTEGRATED N-MOS AND P-MOS DEVICES
    3.
    发明申请
    TECHNIQUES FOR FORMING DUAL-STRAIN FINS FOR CO-INTEGRATED N-MOS AND P-MOS DEVICES 审中-公开

    公开(公告)号：US20190326290A1

    公开(公告)日：2019-10-24

    申请号：US16465039

    申请日：2016-12-29

    Applicant: INTEL CORPORATION

    Inventor： STEPHEN M. CEA ,  RISHABH MEHANDRU ,  ANUPAMA BOWONDER ,  ANAND S. MURTHY ,  TAHIR GHANI

    IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/165 ,  H01L21/02 ,  H01L29/06

    Abstract: Techniques are disclosed for forming dual-strain fins for co-integrated n-MOS and p-MOS devices. The techniques can be used to monolithically form tensile-strained fins to be used for n-MOS devices and compressive-strained fins to be used for p-MOS devices utilizing the same substrate, such that a single integrated circuit (IC) can include both of the devices. In some instances, the oppositely stressed fins may be achieved by employing a relaxed SiGe (rSiGe) layer from which the tensile and compressive-strained material can be formed. In some instances, the techniques include the formation of tensile-stressed Si and/or SiGe fins and compressive-stressed SiGe and/or Ge fins using a single relaxed SiGe layer to enable the co-integration of n-MOS and p-MOS devices, where each set of devices includes preferred materials and preferred stress/strain to enhance their respective performance. In some cases, improvements of at least 25% in drive current can be obtained.

    BURIED ETCH-STOP LAYER TO HELP CONTROL TRANSISTOR SOURCE/DRAIN DEPTH
    4.
    发明申请
    BURIED ETCH-STOP LAYER TO HELP CONTROL TRANSISTOR SOURCE/DRAIN DEPTH 审中-公开

    公开(公告)号：US20200006488A1

    公开(公告)日：2020-01-02

    申请号：US16020361

    申请日：2018-06-27

    Applicant: INTEL CORPORATION

    Inventor： RISHABH MEHANDRU ,  BISWAJEET GUHA ,  ANUPAMA BOWONDER ,  ANAND S. MURTHY ,  TAHIR GHANI ,  STEPHEN M. CEA

    IPC: H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L21/74 ,  H01L29/66

    Abstract: Integrated circuit structures including a buried etch-stop layer to help control transistor source/drain depth are provided herein. The buried etch-stop layer addresses the issue of the source/drain etch (or epi-undercut (EUC) etch) going below the bottom of the active height of the channel region, as such an issue can result in un-controlled sub-fin leakage that causes power consumption degradation and other undesired performance issues. The buried etch-stop layer is formed below the channel material, such as in the epitaxial stack that includes the channel material, and acts to slow the removal of material after the channel material has been removed when etching to form the source/drain trenches. In other words, the buried etch-stop layer includes different material from the channel material that can be etched, for at least one given etchant, at a relatively slower rate than the channel material to help control the source/drain trench depth.

    HIGH MOBILITY STRAINED CHANNELS FOR FIN-BASED NMOS TRANSISTORS
    6.
    发明申请
    HIGH MOBILITY STRAINED CHANNELS FOR FIN-BASED NMOS TRANSISTORS 审中-公开

    公开(公告)号：US20190115466A1

    公开(公告)日：2019-04-18

    申请号：US16214946

    申请日：2018-12-10

    Applicant: INTEL CORPORATION

    Inventor： STEPHEN M. CEA ,  ROZA KOTLYAR ,  HAROLD W. KENNEL ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  WILLY RACHMADY ,  TAHIR GHANI

    IPC: H01L29/78 ,  H01L29/161 ,  H01L29/04 ,  H01L29/06 ,  H01L27/092 ,  H01L29/10 ,  H01L29/66

    Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

    CONVERSION OF STRAIN-INDUCING BUFFER TO ELECTRICAL INSULATOR
    9.
    发明申请
    CONVERSION OF STRAIN-INDUCING BUFFER TO ELECTRICAL INSULATOR 审中-公开
    应变诱导缓冲器对电绝缘子的转换

    公开(公告)号：US20150380481A1

    公开(公告)日：2015-12-31

    申请号：US14844816

    申请日：2015-09-03

    Applicant: INTEL CORPORATION

    Inventor： ANNALISA CAPPELLANI ,  VAN H. LE ,  GLENN A. GLASS ,  KELIN J. KUHN ,  STEPHEN M. CEA

    IPC: H01L29/06

    CPC classification number: H01L29/66795 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02241 ,  H01L21/02255 ,  H01L21/02304 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/306 ,  H01L21/76 ,  H01L21/7624 ,  H01L21/76283 ,  H01L29/0603 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/7378 ,  H01L29/785 ,  H01L33/12 ,  H05K1/18

    Abstract: Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator.

    Abstract translation: 公开了用于将应变诱导半导体缓冲层转化为缓冲层的一个或多个位置处的电绝缘体的技术，从而允许上述器件层具有许多益处，其在一些实施例中包括由于生长而产生的那些 在应变诱导缓冲器上并具有埋入的电绝缘体层。 例如，在非平面集成晶体管电路的Fin和衬底之间具有埋入的电绝缘体层（最初用作制造上述有源器件层期间的应变诱导缓冲器）可以同时使得具有高的低掺杂Fin 移动性，期望的器件静电，以及消除或以其他方式减少衬底结泄漏。 此外，源极和漏极区域下的这种电绝缘体的存在可以进一步显着减少结漏电。 在一些实施例中，基本上整个缓冲层被转换成电绝缘体。

    HIGH MOBILITY STRAINED CHANNELS FOR FIN-BASED NMOS TRANSISTORS
    10.
    发明申请
    HIGH MOBILITY STRAINED CHANNELS FOR FIN-BASED NMOS TRANSISTORS 审中-公开

    公开(公告)号：US20200381549A1

    公开(公告)日：2020-12-03

    申请号：US16998382

    申请日：2020-08-20

    Applicant: INTEL CORPORATION

    Inventor： STEPHEN M. CEA ,  ROZA KOTLYAR ,  HAROLD W. KENNEL ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  WILLY RACHMADY ,  TAHIR GHANI

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/161

    Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

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