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公开(公告)号:US12176292B2
公开(公告)日:2024-12-24
申请号:US18375867
申请日:2023-10-02
Applicant: Intel Corporation
Inventor: Sanka Ganesan , Ram Viswanath , Xavier Francois Brun , Tarek A. Ibrahim , Jason M. Gamba , Manish Dubey , Robert Alan May
IPC: H01L23/538 , H01L23/00 , H01L23/31 , H01L23/367
Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.
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公开(公告)号:US20240027697A1
公开(公告)日:2024-01-25
申请号:US17871558
申请日:2022-07-22
Applicant: Intel Corporation
Inventor: Wesley B. Morgan , Mohanraj Prabhugoud , David Shia , Eric J. M. Moret , Pooya Tadayon , Tarek A. Ibrahim
IPC: G02B6/38
CPC classification number: G02B6/3897 , G02B6/3885 , G02B6/3893
Abstract: Optical connectors with alignment features, and methods of forming the same, are disclosed herein. In one example, an optical ferrule includes holes to couple a fiber array to the optical ferrule, a mating protrusion to mate with an optical receptacle, and alignment features to align the fiber array with optical waveguides in the optical receptacle. The optical receptacle includes the optical waveguides, a mating cavity to mate with the mating protrusion on the optical ferrule, and alignment features to mate with the alignment features on the optical ferrule.
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3.
公开(公告)号:US20230395467A1
公开(公告)日:2023-12-07
申请号:US17833648
申请日:2022-06-06
Applicant: Intel Corporation
Inventor: Srinivas V. Pietambaram , Kristof Darmawikarta , Tarek A. Ibrahim , Jeremy D. Ecton , Brandon Christian Marin , Gang Duan , Suddhasattwa Nad , Yi Yang , Benjamin T. Duong , Junxin Wang , Sameer R. Paital
IPC: H01L23/48 , H01L23/498 , H01L21/48 , H01L21/768 , H05K1/11 , H01L23/00 , H05K3/42 , H05K3/46 , H05K1/03
CPC classification number: H01L23/481 , H01L23/49822 , H01L23/49816 , H01L21/486 , H01L21/76898 , H05K1/112 , H01L24/16 , H05K3/429 , H05K3/4644 , H05K1/0306 , H01L2224/16225
Abstract: In one embodiment, a substrate includes a glass core layer defining a plurality of holes between a first side of the glass core layer and a second side of the glass core layer opposite the first side and a conductive metal inside the holes of the glass core layer. The conductive metal electrically couples the first side of the glass core layer and the second side of the glass core layer. The substrate also includes a dielectric material between the conductive metal and the inside surfaces of the holes of the glass core layer.
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公开(公告)号:US20220399263A1
公开(公告)日:2022-12-15
申请号:US17345912
申请日:2021-06-11
Applicant: Intel Corporation
Inventor: Brandon Christian Marin , Tarek A. Ibrahim , Karumbu Nathan Meyyappan , Valery Ouvarov-Bancalero , Dingying Xu
IPC: H01L23/498 , H01L23/538 , H01L21/48 , H01L23/00 , H01L25/065 , H01L25/18 , H01L25/00
Abstract: A z-disaggregated integrated circuit package substrate assembly comprises a first substrate component (a coreless patch), a second substrate component (a core patch), and a third substrate component (an interposer). The coreless patch comprises thinner dielectric layers and higher density routing and can comprise an embedded bridge to allow for communication between integrated circuit dies attached to the coreless patch. The core layer acts as a middle layer interconnect between the coreless patch and the interposer and comprises liquid metal interconnects to connect the core patch physically and electrically to the coreless patch and the interposer. Core patch through holes comprise liquid metal plugs. Some through holes can be surrounded by and coaxially aligned with magnetic plugs to provide improved power signal delivery. The interposer comprises thicker dielectric layers and lower density routing. The substrate assembly can reduce cost and provide improved overall yield and electrical performance relative to monolithic substrates.
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公开(公告)号:US11302643B2
公开(公告)日:2022-04-12
申请号:US16829396
申请日:2020-03-25
Applicant: Intel Corporation
Inventor: Sanka Ganesan , Ram Viswanath , Xavier Francois Brun , Tarek A. Ibrahim , Jason M. Gamba , Manish Dubey , Robert Alan May
IPC: H01L23/538 , H01L23/367 , H01L23/31 , H01L23/00
Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.
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公开(公告)号:US20250096053A1
公开(公告)日:2025-03-20
申请号:US18470645
申请日:2023-09-20
Applicant: Intel Corporation
Inventor: Jeremy Ecton , Brandon C. Marin , Bohan Shan , Tarek A. Ibrahim , Srinivas V. Pietambaram , Gang Duan , Benjamin T. Duong , Suddhasattwa Nad
IPC: H01L23/15 , H01L23/498 , H01L23/522 , H01L23/538 , H01L25/065
Abstract: A microelectronic assembly includes an embedded bridge die and a glass structure, such as glass patch, under the bridge die. The bridge die and the glass structure are embedded in a substrate. The assembly may further include two or more dies arranged over the substrate and coupled to the bridge die. The glass structure may include through-glass vias, and vias in the substrate below the glass structure are self-aligned to the through-glass vias. The glass structure may include an embedded passive device, such as an embedded inductor or capacitor.
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公开(公告)号:US12068172B2
公开(公告)日:2024-08-20
申请号:US16525985
申请日:2019-07-30
Applicant: Intel Corporation
Inventor: Tarek A. Ibrahim , Rahul N. Manepalli , Wei-Lun K. Jen , Steve S. Cho , Jason M. Gamba , Javier Soto Gonzalez
IPC: H01L23/498 , H01L21/48 , H01L23/538
CPC classification number: H01L21/4846 , H01L21/481 , H01L23/49838 , H01L23/5386 , H01L23/5385 , H01L2224/16225 , H01L2924/19041 , H01L2924/19105
Abstract: Embodiments disclosed herein include electronic packages and methods of making electronic packages. In an embodiment, the electronic package comprises a package substrate, an array of first level interconnect (FLI) bumps on the package substrate, wherein each FLI bump comprises a surface finish, a first pad on the package substrate, wherein the first pad comprises the surface finish, and wherein a first FLI bump of the array of FLI bumps is electrically coupled to the first pad, and a second pad on the package substrate, wherein the second pad is electrically coupled to the first pad.
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8.
公开(公告)号:US20240186250A1
公开(公告)日:2024-06-06
申请号:US18061188
申请日:2022-12-02
Applicant: Intel Corporation
Inventor: Jeremy D. Ecton , Brandon Christian Marin , Srinivas V. Pietambaram , Tarek A. Ibrahim , Suddhasattwa Nad , Gang Duan , Haobo Chen , Hiroki Tanaka
IPC: H01L23/538 , H01L21/48
CPC classification number: H01L23/5381 , H01L21/486 , H01L23/5384 , H01L23/5386
Abstract: A microelectronic assembly includes a substrate comprising: a panel including glass and defining an opening therein; an interconnect bridge (IB) in the opening and including interconnect pathways and IB through vias (IBTVs); and electrically conductive structures at a lower surface of the substrate to electrically couple the substrate to another component, at least some of the electrically conductive structures coupled to the IBTVs to form respective vertical electrical connections between the lower surface of the substrate and an upper surface of the substrate; and an electronic component (EC) layer on the upper surface of the substrate, the EC layer including a first active EC (AEC) and a second AEC electrically coupled to one another through the interconnect pathways, at least one of the first AEC or the second AECs further electrically coupled to one or more of the at least some of the electrically conductive structures.
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9.
公开(公告)号:US20230395445A1
公开(公告)日:2023-12-07
申请号:US17833650
申请日:2022-06-06
Applicant: Intel Corporation
Inventor: Srinivas V. Pietambaram , Kristof Darmawikarta , Tarek A. Ibrahim , Jeremy D. Ecton , Brandon Christian Marin , Gang Duan , Suddhasattwa Nad , Yi Yang , Benjamin T. Duong , Junxin Wang , Sameer R. Paital
IPC: H01L23/15 , H01L23/498 , H01L21/48 , H05K1/03 , H05K3/40
CPC classification number: H01L23/15 , H01L23/49827 , H01L21/486 , H05K1/0306 , H05K3/4061
Abstract: In one embodiment, a substrate includes a glass core layer defining a plurality of holes between a first side of the glass core layer and a second side of the glass core layer opposite the first side and a conductive metal inside the holes of the glass core layer. The conductive metal electrically couples the first side of the glass core layer and the second side of the glass core layer. The substrate also includes a dielectric material between the conductive metal and the inside surfaces of the holes of the glass core layer.
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公开(公告)号:US20230197697A1
公开(公告)日:2023-06-22
申请号:US17552581
申请日:2021-12-16
Applicant: Intel Corporation
Inventor: Srinivas V. Pietambaram , Tarek A. Ibrahim , Rahul N. Manepalli , John S. Guzek , Hamid Azimi
IPC: H01L25/16 , H01L23/15 , H01L23/498 , H01L49/02 , H01L23/00
CPC classification number: H01L25/16 , H01L23/15 , H01L23/49827 , H01L28/60 , H01L23/49811 , H01L24/16 , H01L2224/16227
Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a glass substrate, having a surface, including a through-glass-substrate via (TGV) and a cavity on the surface; a first die nested in the cavity; an insulating material on the surface of the glass substrate; a first conductive pillar and a second conductive pillar through the insulating material; a capacitor, in the insulating material, including a first conductive layer, on the surface of the glass substrate, electrically coupled to the TGV and the first conductive pillar forming a first plate of the capacitor, a dielectric layer on the first conductive layer; and a second conductive layer, on the dielectric layer, electrically coupled to the second conductive pillar forming a second plate of the capacitor; and a second die, on the insulating material, electrically coupled to the first die.
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