公开(公告)号：US20150163904A1

公开(公告)日：2015-06-11

申请号：US14102757

申请日：2013-12-11

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  John S. Guzek ,  Johanna M. Swan ,  Christopher J. Nelson ,  Nitin A. Deshpande ,  William J. Lambert ,  Charles A. Gealer ,  Feras Eid ,  Islam A. Salama ,  Kemal Aygun ,  Sasha N. Oster ,  Tyler N. Osborn

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/40 ,  G06F1/18

CPC classification number: H01L25/16 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/50 ,  H01L24/86 ,  H01L25/00 ,  H01L25/0655 ,  H01L2224/0405 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/29078 ,  H01L2224/86203 ,  H01L2224/86815 ,  H05K1/185 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.

Abstract translation: 本说明书的微电子封装可以包括具有与其电连接的至少一行连接结构的第一微电子器件和具有与其电连接的至少一排连接结构的第二微电子器件，其中所述至少一个 第一微电子器件行与X方向上的至少一个第二微电子器件行内的对应连接结构对准。 包括具有在互连衬底的第一表面上沿x方向延伸的多个电隔离导电迹线的互连衬底的互连可以附接到所述至少一个第一微电子器件连接结构行和所述至少一个第二微电子器件 连接结构行，使得至少一个互连导电迹线形成第一微电子器件连接结构与其对应的第二微电子器件连接结构之间的连接。

公开(公告)号：US20160260679A1

公开(公告)日：2016-09-08

申请号：US14430131

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： Kabirkumar J. Mirpuri ,  Hongjin Jiang ,  Tyler N. Osborn ,  Rajen S. Sidhu ,  Ibrahim Bekar ,  Susheel G. Jadhav

IPC: H01L23/00

CPC classification number: H01L24/73 ,  H01L21/4867 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/0569 ,  H01L2224/11 ,  H01L2224/13014 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/29026 ,  H01L2224/29109 ,  H01L2224/29113 ,  H01L2224/73104 ,  H01L2224/92143 ,  H01L2924/014

Abstract: Apparatuses, processes, and systems related to an interconnect with an increased z-height and decreased reflow temperature are described herein. In embodiments, an interconnect may include a solder ball and a solder paste to couple the solder ball to a substrate. The solder ball and/or solder paste may be comprised of an alloy with a relatively low melting point and an alloy with a relatively high melting point.

Abstract translation: 这里描述了与具有增加的z高度和降低的回流温度的互连相关的装置，工艺和系统。 在实施例中，互连可以包括焊球和焊膏以将焊球耦合到衬底。 焊球和/或焊膏可以由具有较低熔点的合金和具有较高熔点的合金构成。

公开(公告)号：US09397071B2

公开(公告)日：2016-07-19

申请号：US14102757

申请日：2013-12-11

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  John S. Guzek ,  Johanna M. Swan ,  Christopher J. Nelson ,  Nitin A. Deshpande ,  William J. Lambert ,  Charles A. Gealer ,  Feras Eid ,  Islam A. Salama ,  Kemal Aygun ,  Sasha N. Oster ,  Tyler N. Osborn

IPC: H05K7/00 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H05K1/18

CPC classification number: H01L25/16 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/50 ,  H01L24/86 ,  H01L25/00 ,  H01L25/0655 ,  H01L2224/0405 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/29078 ,  H01L2224/86203 ,  H01L2224/86815 ,  H05K1/185 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.

Abstract translation: 本说明书的微电子封装可以包括具有与其电连接的至少一行连接结构的第一微电子器件和具有与其电连接的至少一排连接结构的第二微电子器件，其中所述至少一个 第一微电子器件行与X方向上的至少一个第二微电子器件行内的对应连接结构对准。 包括具有在互连衬底的第一表面上沿x方向延伸的多个电隔离导电迹线的互连衬底的互连可以附接到所述至少一个第一微电子器件连接结构行和所述至少一个第二微电子器件 连接结构行，使得至少一个互连导电迹线形成第一微电子器件连接结构与其对应的第二微电子器件连接结构之间的连接。

公开(公告)号：US20150108204A1

公开(公告)日：2015-04-23

申请号：US14581985

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Tieyu Zheng ,  Sumit Kumar ,  Sridhar Nara ,  Renee D. Garcia ,  Manohar S. Konchady ,  Suresh B. Yeruva ,  Lynn H. Chen ,  Tyler N. Osborn ,  Sairam Agraharam

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/0603 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/1413 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/2064 ,  H01L2924/20643 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014

Abstract: An integrated circuit (IC) package stack with a first and second substrate interconnected by solder further includes solder resist openings (SRO) of mixed lateral dimension are spatially varied across an area of the substrates. In embodiments, SRO dimension is varied between at least two different diameters as a function of an estimated gap between the substrates that is dependent on location within the substrate area. In embodiments where deflection in at least one substrate reduces conformality between the substrates, a varying solder joint height is provided from a fixed volume of solder by reducing the lateral dimensioning of the SRO in regions of larger gap relative to SRO dimensions in regions of smaller gap. In embodiments, the first substrate may be any of an IC chip, package substrate, or interposer while the second substrate may be any of another IC chip, package substrate, interposer, or printed circuit board (PCB).

Abstract translation: 具有通过焊料互连的第一和第二衬底的集成电路（IC）封装堆栈还包括混合侧向尺寸的阻焊剂开口（SRO）在衬底的一个区域上空间变化。 在实施例中，SRO尺寸在至少两个不同直径之间变化，作为取决于衬底区域内的位置的衬底之间的估计间隙的函数。 在至少一个衬底中的偏转减小衬底之间的共形性的实施例中，通过在较小间隙的区域中相对于SRO尺寸的较大间隙的区域中减小SRO的横向尺寸，从固定体积的焊料提供变化的焊点高度 。 在实施例中，第一基板可以是IC芯片，封装基板或插入件中的任何一个，而第二基板可以是另一个IC芯片，封装基板，插入件或印刷电路板（PCB）中的任何一个。

公开(公告)号：US09842832B2

公开(公告)日：2017-12-12

申请号：US15183179

申请日：2016-06-15

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  John S. Guzek ,  Johanna M. Swan ,  Christopher J. Nelson ,  Nitin A. Deshpande ,  William J. Lambert ,  Charles A. Gealer ,  Feras Eid ,  Islam A. Salama ,  Kemal Aygun ,  Sasha N. Oster ,  Tyler N. Osborn

IPC: H01L25/16 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H05K1/18

CPC classification number: H01L25/16 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/50 ,  H01L24/86 ,  H01L25/00 ,  H01L25/0655 ,  H01L2224/0405 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/29078 ,  H01L2224/86203 ,  H01L2224/86815 ,  H05K1/185 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.

公开(公告)号：US20160300824A1

公开(公告)日：2016-10-13

申请号：US15183179

申请日：2016-06-15

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  John S. Guzek ,  Johanna M. Swan ,  Christopher J. Nelson ,  Nitin A. Deshpande ,  William J. Lambert ,  Charles A. Gealer ,  Feras Eid ,  Islam A. Salama ,  Kemal Aygun ,  Sasha N. Oster ,  Tyler N. Osborn

IPC: H01L25/16 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/16 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/50 ,  H01L24/86 ,  H01L25/00 ,  H01L25/0655 ,  H01L2224/0405 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/29078 ,  H01L2224/86203 ,  H01L2224/86815 ,  H05K1/185 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.

公开(公告)号：US09312237B2

公开(公告)日：2016-04-12

申请号：US14581985

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Tieyu Zheng ,  Sumit Kumar ,  Sridhar Nara ,  Renee D. Garcia ,  Manohar S. Konchady ,  Suresh B. Yeruva ,  Lynn H. Chen ,  Tyler N. Osborn ,  Sairam Agraharam

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/0603 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/1413 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/2064 ,  H01L2924/20643 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014

Abstract: An integrated circuit (IC) package stack with a first and second substrate interconnected by solder further includes solder resist openings (SRO) of mixed lateral dimension are spatially varied across an area of the substrates. In embodiments, SRO dimension is varied between at least two different diameters as a function of an estimated gap between the substrates that is dependent on location within the substrate area. In embodiments where deflection in at least one substrate reduces conformality between the substrates, a varying solder joint height is provided from a fixed volume of solder by reducing the lateral dimensioning of the SRO in regions of larger gap relative to SRO dimensions in regions of smaller gap. In embodiments, the first substrate may be any of an IC chip, package substrate, or interposer while the second substrate may be any of another IC chip, package substrate, interposer, or printed circuit board (PCB).