公开(公告)号：US20240005997A1

公开(公告)日：2024-01-04

申请号：US18181140

申请日：2023-03-09

Applicant: Kioxia Corporation

Inventor： Hidehiro SHIGA

IPC: G11C16/16 ,  G11C16/04

CPC classification number: G11C16/16 ,  G11C16/0483

Abstract: Disclosed herein are related to a memory device and a method of operating the memory device. In one aspect, a voltage supply circuit is configured to apply, during a first time period, a first voltage to a gate of a first switch transistor connected to a first block of memory cells through a first word line to enable the first switch transistor. In one aspect, the voltage supply circuit is configured to apply, during the first time period, a second voltage lower than the first voltage to the first word line through the first switch transistor. In one aspect, the voltage supply circuit is configured to apply, during the first time period, a third voltage lower than the second voltage to a gate of a second switch transistor connected to a second block of memory cells through a second word line to disable the second switch transistor.

公开(公告)号：US20230284460A1

公开(公告)日：2023-09-07

申请号：US17899898

申请日：2022-08-31

Applicant: KIOXIA CORPORATION

Inventor： Tomoki CHIBA ,  Daisaburo TAKASHIMA ,  Hidehiro SHIGA

IPC: H01L27/24 ,  H01L27/22 ,  H01L45/00 ,  G11C11/16 ,  G11C13/00

CPC classification number: H01L27/2454 ,  H01L27/228 ,  H01L27/249 ,  H01L45/06 ,  H01L45/126 ,  H01L45/144 ,  H01L45/146 ,  H01L45/143 ,  G11C11/1673 ,  G11C13/004 ,  G11C2213/71

Abstract: A variable resistance non-volatile memory includes a semiconductor substrate, a first electrode line extending in a first direction away from the semiconductor substrate, a second electrode line extending in the first direction parallel to the first electrode line, an insulating film between the first and second electrode lines, a variable resistance film formed on the first electrode line, a low electrical resistance layer formed on the variable resistance film and having a lower electrical resistance than the variable resistance film, a semiconductor film in contact with the low electrical resistance layer and the insulating film, and formed on opposite surfaces of the second electrode line, a gate insulator film extending in the first direction and in contact with the semiconductor film, and a voltage application electrode that extends in a second direction that crosses the first direction, and is in contact with the gate insulator film.

公开(公告)号：US20230197148A1

公开(公告)日：2023-06-22

申请号：US17806346

申请日：2022-06-10

Applicant: Kioxia Corporation

Inventor： Rieko FUNATSUKI ,  Takashi MAEDA ,  Hidehiro SHIGA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C11/5642 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/0483 ,  G11C16/3459

Abstract: A semiconductor memory device includes i first word lines connected to the i first memory cells, i second word lines connected to the i second memory cells, a driver capable of supplying voltage to each of the i first word lines and each of the i second word lines, and a logic control circuit controlling both a write operation including a verify operation and a read operation including a verify operation. In the semiconductor memory device, when an order of performing a sense operation for determining whether or not a threshold voltage of the k-th first memory cell has reached a j-th threshold voltage in the verify operation is different from that of in the read operation, a voltage applied to the k-th first word line in the verify operation is different from a voltage applied to the k-th first word line in the read operation.

公开(公告)号：US20230064982A1

公开(公告)日：2023-03-02

申请号：US17679959

申请日：2022-02-24

Applicant: KIOXIA CORPORATION

Inventor： Hidehiro SHIGA ,  Daisaburo TAKASHIMA

IPC: G11C13/00

Abstract: A memory device includes a memory cell array including a select transistor and a plurality of memory cells connected in series, each memory cell including a cell transistor and a variable resistance layer connected in parallel. During a write operation, a voltage setting circuit is controlled to apply a first voltage to a selected word line and a second voltage to non-selected word lines. The time period for applying the first voltage to the selected word line starts later than the time period for applying the second voltage to the non-selected word lines and ends earlier than the time period for applying the second voltage to the non-selected word lines.

公开(公告)号：US20230078441A1

公开(公告)日：2023-03-16

申请号：US17689182

申请日：2022-03-08

Applicant: Kioxia Corporation

Inventor： Reiko SUMI ,  Takashi MAEDA ,  Hidehiro SHIGA

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10

Abstract: A semiconductor memory device of embodiments includes that in a write operation, the driver applies a first voltage to the first select gate line, applies a second voltage lower than the first voltage to the second select gate line, applies a third voltage equal to or higher than the first voltage to the first dummy word line on an uppermost layer, applies a fourth voltage different from the third voltage and higher than the second voltage to the second dummy word line on an uppermost layer, applies a fifth voltage equal to or higher than the third voltage to the first dummy word line on a lowermost layer, and applies a sixth voltage different from the fifth voltage and equal to or higher than the fourth voltage to the second dummy word line on a lowermost layer.

公开(公告)号：US20220180942A1

公开(公告)日：2022-06-09

申请号：US17458059

申请日：2021-08-26

Applicant: KIOXIA CORPORATION

Inventor： Kazutaka IKEGAMI ,  Hidehiro SHIGA ,  Takashi MAEDA ,  Rieko FUNATSUKI ,  Takayuki MIYAZAKI

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/20 ,  G11C16/30

Abstract: A semiconductor storage device includes a semiconductor pillar, a first string having first memory cells connected in series, first word lines connected to the first memory cells, a second string having second memory cells connected in series, and second word lines connected to the second memory cells. Each of the first memory cells faces, and shares a channel in the semiconductor pillar with, one of the second memory cells. When reading data of the k-th first memory cell, a voltage of the first word line connected to the k-th first memory cell reaches a first voltage at a first timing, and a voltage of the second word line connected to at least one of the second memory cells other than the k-th second memory cell in the second string facing the k-th first memory cell reaches the first voltage at a second timing that is later than the first timing.

公开(公告)号：US20210280257A1

公开(公告)日：2021-09-09

申请号：US17009376

申请日：2020-09-01

Applicant: KIOXIA CORPORATION

Inventor： Hidehiro SHIGA ,  Takashi MAEDA

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/24 ,  G11C16/08 ,  G11C16/04 ,  G11C16/30

Abstract: A nonvolatile semiconductor storage device includes a first channel layer including a first drain-side select transistor, a first source-side select transistor, and a first memory cell transistor, a second channel layer including a second drain-side select transistor, a second source-side select transistor, and a second memory cell transistor, a word line that functions as a gate electrode of the first and second memory cell transistors, and a controller. When a read operation is executed on the first memory cell transistor, the controller turns on the second drain-side select transistor and the second source-side select transistor, supplies a first voltage to the word line in a state where the first drain-side select transistor and the first source-side select transistor are turned off, and then, supplies a second voltage to the word line in a state where the first drain-side select transistor and the first source-side select transistor are turned on.

公开(公告)号：US20210158876A1

公开(公告)日：2021-05-27

申请号：US17016580

申请日：2020-09-10

Applicant: Kioxia Corporation

Inventor： Hiroshi MAEJIMA ,  Hidehiro SHIGA ,  Masaki KONDO

IPC: G11C16/26 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/34

Abstract: A semiconductor memory device includes separate first and second word lines respectively facing first and second portions of a semiconductor and sandwiching the semiconductor; and first and second cell transistors respectively located in the first and second portions and respectively coupled to the first and second word lines. In a first operation, a first read is executed on the second cell transistor while a first voltage and a higher second voltage are being respectively applied to the first and second word lines. In a second operation, a second read is executed on the first cell transistor while a third voltage between the first and second voltages is being applied to the second word line.

公开(公告)号：US20240096413A1

公开(公告)日：2024-03-21

申请号：US18177704

申请日：2023-03-02

Applicant: Kioxia Corporation

Inventor： Natsuki SAKAGUCHI ,  Takashi MAEDA ,  Rieko FUNATSUKI ,  Hidehiro SHIGA

IPC: G11C16/04 ,  G11C7/06 ,  G11C16/24

CPC classification number: G11C16/0433 ,  G11C7/065 ,  G11C16/24

Abstract: A control circuit of a semiconductor memory device performs a write operation on a memory cell transistor of the semiconductor memory device by performing a first pulse application operation of lowering a threshold voltage of the memory cell transistor, a precharge operation, and then a second pulse application operation. In the precharge operation, in a state in which first and second select transistors connected to the memory cell transistor are turned on, a bit line connected to the memory cell transistor is charged by applying a ground voltage to a word line connected to a gate of the memory cell transistor and applying a voltage higher than the ground voltage to a source line. In the second pulse application operation, in a state in which the first select transistor is turned on and the second select transistor is turned off, a program voltage is applied to the word line.

公开(公告)号：US20240038279A1

公开(公告)日：2024-02-01

申请号：US18359355

申请日：2023-07-26

Applicant: Kioxia Corporation

Inventor： Ryu OGIWARA ,  Hidehiro SHIGA ,  Daisaburo TAKASHIMA

IPC: G11C5/06 ,  G11C5/02 ,  H10B63/00

CPC classification number: G11C5/063 ,  G11C5/025 ,  H10B63/84 ,  H10B63/34

Abstract: According to one embodiment, in a semiconductor memory device, multiple first memory cells are connected in parallel between a first local bit line and a local source line. Multiple second memory cells are connected in parallel between a second local bit line and the local source line. Each of the multiple first memory cells includes a first cell transistor and a first resistance change element connected in series. Each of the multiple second memory cells includes a second cell transistor and a second resistance change element connected in series. A first selection gate line extends in a second direction across multiple cell blocks arranged in the second direction. A second selection gate line is placed on the opposite side of the first selection gate line with the local source line interposed therebetween. The second selection gate line extends in the second direction across multiple cell blocks arranged in the second direction.