利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

47 条记录 (耗时 0.02 秒)

    Method of improving the wafer-to-wafer thickness uniformity of silicon nitride layers
    1.
    发明授权
    Method of improving the wafer-to-wafer thickness uniformity of silicon nitride layers 有权
    提高氮化硅层的晶片到晶片厚度均匀性的方法

    公开(公告)号：US08084088B2

    公开(公告)日：2011-12-27

    申请号：US10881932

    申请日：2004-06-30

    申请人： Katja Huy ,  Hartmut Ruelke ,  Michael Turner

    发明人： Katja Huy ,  Hartmut Ruelke ,  Michael Turner

    IPC分类号： C23C16/00

    CPC分类号： H01L21/02274 ,  C23C16/345 ,  C23C16/4405 ,  H01L21/0217 ,  H01L21/3185

    摘要： Wafer-to-wafer thickness uniformity may be improved significantly in a process for depositing a silicon nitride layer in that the flow rate of the reactant and the chamber pressure are varied during a deposition cycle. By correspondingly adapting the flow rate and/or the chamber pressure before and after the actual deposition step, the process conditions may be more effectively stabilized, thereby reducing process variations, even after non-deposition phases of the deposition tool, such as a preceding plasma clean process or an idle period of the tool.

    摘要翻译： 在沉积氮化硅层的过程中，可以显着改善晶片对晶片的厚度均匀性，因为反应物的流速和室压力在沉积循环期间是变化的。 通过相应地适应实际沉积步骤之前和之后的流速和/或室压力，可以更有效地稳定工艺条件，从而即使在沉积工具的非沉积阶段（例如先前的等离子体）之后也减少工艺变化 清洁过程或工具的空闲期间。

    Method of improving the wafer-to-wafer thickness uniformity of silicon nitride layers
    2.
    发明申请
    Method of improving the wafer-to-wafer thickness uniformity of silicon nitride layers 有权
    提高氮化硅层的晶片到晶片厚度均匀性的方法

    公开(公告)号：US20050026434A1

    公开(公告)日：2005-02-03

    申请号：US10881932

    申请日：2004-06-30

    申请人： Katja Huy ,  Hartmut Ruelke ,  Michael Turner

    发明人： Katja Huy ,  Hartmut Ruelke ,  Michael Turner

    IPC分类号： C23C16/34 ,  C23C16/44 ,  H01L21/318 ,  H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/02274 ,  C23C16/345 ,  C23C16/4405 ,  H01L21/0217 ,  H01L21/3185

    摘要： Wafer-to-wafer thickness uniformity may be improved significantly in a process for depositing a silicon nitride layer in that the flow rate of the reactant and the chamber pressure are varied during a deposition cycle. By correspondingly adapting the flow rate and/or the chamber pressure before and after the actual deposition step, the process conditions may be more effectively stabilized, thereby reducing process variations, even after non-deposition phases of the deposition tool, such as a preceding plasma clean process or an idle period of the tool.

    摘要翻译： 在沉积氮化硅层的过程中，可以显着改善晶片对晶片的厚度均匀性，因为反应物的流速和室压力在沉积循环期间是变化的。 通过相应地适应实际沉积步骤之前和之后的流速和/或室压力，可以更有效地稳定工艺条件，从而即使在沉积工具的非沉积阶段（例如先前的等离子体）之后也减少工艺变化 清洁过程或工具的空闲期间。

    Enhanced adhesion of PECVD carbon on dielectric materials by providing an adhesion interface
    7.
    发明授权
    Enhanced adhesion of PECVD carbon on dielectric materials by providing an adhesion interface 有权
    通过提供粘合界面来增强PECVD碳对介电材料的粘附

    公开(公告)号：US08415257B2

    公开(公告)日：2013-04-09

    申请号：US12898822

    申请日：2010-10-06

    申请人： Hartmut Ruelke ,  Volker Jaschke

    发明人： Hartmut Ruelke ,  Volker Jaschke

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/31144 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/3105 ,  H01L21/3146 ,  H01L21/32139

    摘要： Amorphous carbon material may be deposited with superior adhesion on dielectric materials, such as TEOS based silicon oxide materials, in complex semiconductor devices by applying a plasma treatment, such as an argon treatment and/or forming a thin adhesion layer based on silicon dioxide, carbon-doped silicon dioxide, prior to depositing the carbon material. Consequently, the hard mask concept based on amorphous carbon may be applied with an increased degree of flexibility, since a superior adhesion may allow a higher degree of flexibility in selecting appropriate deposition parameters for the carbon material.

    摘要翻译： 非晶碳材料可以通过施加诸如氩处理的等离子体处理和/或形成基于二氧化硅，碳的薄粘合层，在复杂的半导体器件中沉积具有优异的电介质材料（例如基于TEOS的氧化硅材料）的附着力 在沉积碳材料之前，将二氧化硅掺杂。 因此，基于无定形碳的硬掩模概念可以被应用于增加的柔性程度，因为优异的粘附性可以允许在为碳材料选择合适的沉积参数时具有更高的灵活性。

    NON-INSULATING STRESSED MATERIAL LAYERS IN A CONTACT LEVEL OF SEMICONDUCTOR DEVICES
    8.
    发明申请
    NON-INSULATING STRESSED MATERIAL LAYERS IN A CONTACT LEVEL OF SEMICONDUCTOR DEVICES 有权
    接触层半导体器件中的非绝缘应力层

    公开(公告)号：US20100327362A1

    公开(公告)日：2010-12-30

    申请号：US12823660

    申请日：2010-06-25

    申请人： Ralf Richter ,  Hartmut Ruelke ,  Joerg Hohage

    发明人： Ralf Richter ,  Hartmut Ruelke ,  Joerg Hohage

    IPC分类号： H01L27/088 ,  H01L21/768

    CPC分类号： H01L21/84 ,  H01L21/823412 ,  H01L21/823425 ,  H01L29/7843

    摘要： In sophisticated semiconductor devices, non-insulating materials with extremely high internal stress level may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors, wherein the non-insulating material may be appropriately “encapsulated” by dielectric material. Consequently, a desired high strain level may be obtained on the basis of a reduced layer thickness, while still providing the insulating characteristics required in the contact level.

    摘要翻译： 在复杂的半导体器件中，可以在接触电平中使用具有非常高的内部应力水平的非绝缘材料，以便增强诸如场效应晶体管的电路元件的性能，其中非绝缘材料可以被适当地“封装” 介电材料。 因此，可以基于减小的层厚度获得期望的高应变水平，同时仍然提供接触水平所需的绝缘特性。

    Method of forming a field effect transistor having a stressed channel region
    10.
    发明申请
    Method of forming a field effect transistor having a stressed channel region 有权
    形成具有应力沟道区域的场效应晶体管的方法

    公开(公告)号：US20060113641A1

    公开(公告)日：2006-06-01

    申请号：US11177774

    申请日：2005-07-08

    申请人： Joerg Hohage ,  Hartmut Ruelke ,  Kai Frohberg

    发明人： Joerg Hohage ,  Hartmut Ruelke ,  Kai Frohberg

    IPC分类号： H01L23/58 ,  H01L21/302

    CPC分类号： H01L29/7833 ,  H01L21/823412 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/7843

    摘要： A semiconductor structure comprises a transistor element formed in a substrate. A stressed layer is formed over the transistor element. The stressed layer has a predetermined compressive intrinsic stress having an absolute value of about 1 GPa or more. Due to this high intrinsic stress, the stressed layer exerts considerable elastic forces to the channel region of the transistor element. Thus, compressive stress is created in the channel region. The compressive stress leads to an increase of the mobility of holes in the channel region.

    摘要翻译： 半导体结构包括形成在衬底中的晶体管元件。 应力层形成在晶体管元件上。 应力层具有绝对值为约1GPa以上的预定压缩本征应力。 由于这种高的固有应力，应力层对晶体管元件的沟道区域施加相当大的弹性力。 因此，在通道区域中产生压应力。 压缩应力导致通道区域中孔的迁移率的增加。