公开(公告)号：US20220223552A1

公开(公告)日：2022-07-14

申请号：US17695654

申请日：2022-03-15

Applicant: Kioxia Corporation

Inventor： Yasuhito YOSHIMIZU ,  Takashi FUKUSHIMA ,  Tatsuro HITOMI ,  Arata INOUE ,  Masayuki MIURA ,  Shinichi KANNO ,  Toshio FUJISAWA ,  Keisuke NAKATSUKA ,  Tomoya SANUKI

IPC: H01L23/00 ,  H01L23/544 ,  G06F11/07

Abstract: A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.

公开(公告)号：US20230324455A1

公开(公告)日：2023-10-12

申请号：US18209398

申请日：2023-06-13

Applicant: Kioxia Corporation

Inventor： Tatsuro HITOMI ,  Yasuhito YOSHIMIZU ,  Masayuki MIURA ,  Arata INOUE ,  Hiroyuki DOHMAE ,  Koichi NAKAZAWA ,  Mitoshi MIYAOKA ,  Kazuhito HAYASAKA ,  Tomoya SANUKI

IPC: G01R31/28 ,  G01R1/073

CPC classification number: G01R31/2886 ,  G01R1/07342

Abstract: According to one embodiment, a wafer includes a substrate including a first region and a second region that do not overlap each other; a first chip unit and a second chip unit each arranged on the substrate; a first electrode and a second electrode each electrically connected to the first chip unit; and a third electrode and a fourth electrode each electrically connected to the second chip unit. The first electrode and the third electrode are arranged in the first region. The second electrode and the fourth electrode are arranged in the second region. The first region is independent of a region in which the first chip unit and the second chip unit are provided.

公开(公告)号：US20230282289A1

公开(公告)日：2023-09-07

申请号：US17899447

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Tomoya SANUKI ,  Hitomi TANAKA ,  Tatsuro HITOMI ,  Yasuhito YOSHIMIZU ,  Masayuki MIURA ,  Yoshihiro OHBA

IPC: G11C16/26 ,  G11C16/34 ,  G06F3/06 ,  H01L27/11563

CPC classification number: G11C16/26 ,  G06F3/0679 ,  G11C16/34 ,  H01L27/11563

Abstract: A method of processing a memory system that includes a substrate with a connector and a semiconductor memory chip connected to the connector is provided. The method includes detaching the semiconductor memory chip from the connector, performing an annealing process with respect to the semiconductor memory chip detached from the connector, and after the annealing process, attaching the semiconductor memory chip to the connector on the substrate.

公开(公告)号：US20230065159A1

公开(公告)日：2023-03-02

申请号：US17984309

申请日：2022-11-10

Applicant: Kioxia Corporation

Inventor： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA ,  Marie TAKADA ,  Masamichi FUJIWARA ,  Kazumasa YAMAMOTO ,  Naoaki KOKUBUN ,  Tatsuro HITOMI ,  Hironori UCHIKAWA

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/11 ,  H03M13/37 ,  H03M13/29 ,  H03M13/15

Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.

公开(公告)号：US20240428875A1

公开(公告)日：2024-12-26

申请号：US18749161

申请日：2024-06-20

Applicant: Kioxia Corporation

Inventor： Tomoya SANUKI ,  Hitomi TANAKA ,  Hajime SANO ,  Tatsuro HITOMI ,  Yasuhito YOSHIMIZU ,  Kazuma HASEGAWA

IPC: G11C29/38 ,  G06F13/16

Abstract: A system includes a rack, a heat treatment device configured to perform a heat treatment, one or more conveyance devices, and a host. The host is configured to determine a target memory chip to be subjected to the heat treatment by the heat treatment device among memory chips in a plurality of drives mounted on the rack, and disable communication with a target drive on which the target memory chip is mounted. The host is configured to control the conveyance devices to dismount the target drive from the rack, detach a component including the target memory chip from the target drive, convey the detached component to the heat treatment device, reattach the component including the target memory chip that has undergone the heat treatment to a drive, and mount the drive with the component including the target memory chip that has undergone the heat treatment on the rack.

公开(公告)号：US20240014062A1

公开(公告)日：2024-01-11

申请号：US18371669

申请日：2023-09-22

Applicant: Kioxia Corporation

Inventor： Tatsuro HITOMI ,  Yasuhito YOSHIMIZU ,  Arata INOUE ,  Hiroyuki DOHMAE ,  Kazuhito HAYASAKA ,  Tomoya SANUKI

IPC: H01L21/677

CPC classification number: H01L21/67781 ,  H01L21/67766 ,  H01L21/67769 ,  H01L21/6773 ,  H01L21/68

Abstract: According to one embodiment, when a first case-mounted memory device that includes a first memory device is not connected to a slot of a host apparatus and is stored in a second stocker, the host apparatus causes a second transport device to transport the first case-mounted memory device to the slot, and to connect it thereto. When the first case-mounted memory device is not connected to the slot and is not stored in the second stocker, the host apparatus causes a first transport device to transport the first memory device from a first stocker to a mounter, causes the mounter to mount the first memory device in a case, and causes the second transport device to transport the first case-mounted memory device to the slot and to connect it thereto.

公开(公告)号：US20240014061A1

公开(公告)日：2024-01-11

申请号：US18371536

申请日：2023-09-22

Applicant: Kioxia Corporation

Inventor： Tatsuro HITOMI ,  Yasuhito YOSHIMIZU ,  Arata INOUE ,  Hiroyuki DOHMAE ,  Kazuhito HAYASAKA ,  Tomoya SANUKI

IPC: H01L21/677 ,  H01L21/67 ,  G01R1/073 ,  G01R1/067 ,  H01L21/66

CPC classification number: H01L21/67769 ,  H01L21/67248 ,  H01L21/67781 ,  H01L21/6773 ,  G01R1/07314 ,  G01R1/06755 ,  H01L22/32

Abstract: According to one embodiment, a cassette housing includes a storage unit, a probe card, and a container. The storage unit stores a semiconductor wafer including a plurality of nonvolatile memory chips. The probe card includes a probe. The probe is configured to be brought into contact with a pad electrode provided on the semiconductor wafer. The container contains heat transfer fluid for lowering or raising temperature of one or both of the probe card and the semiconductor wafer stored in the storage unit.

公开(公告)号：US20220204270A1

公开(公告)日：2022-06-30

申请号：US17694532

申请日：2022-03-14

Applicant: Kioxia Corporation

Inventor： Yasuhito YOSHIMIZU ,  Takashi FUKUSHIMA ,  Tatsuro HITOMI ,  Arata INOUE ,  Masayuki MIURA ,  Shinichi KANNO ,  Toshio FUJISAWA ,  Keisuke NAKATSUKA ,  Tomoya SANUKI

IPC: B65G1/137

Abstract: According to one embodiment, a storage device includes a control apparatus and a stocker. The control apparatus writes data to or reads data from a storage medium that includes a plurality of non-volatile memory chips. The stocker stores a plurality of the storage media that are detached from the control apparatus. The control apparatus includes a first temperature control system. The first temperature control system raises temperature of the storage medium to a first temperature or higher. The stocker includes a second temperature control system. The second temperature control system cools the storage medium to a second temperature or lower. The second temperature is lower than the first temperature.

公开(公告)号：US20210149568A1

公开(公告)日：2021-05-20

申请号：US17121024

申请日：2020-12-14

Applicant: Kioxia Corporation

Inventor： Yasuhito YOSHIMIZU ,  Takashi FUKUSHIMA ,  Tatsuro HITOMI ,  Arata INOUE ,  Masayuki MIURA ,  Shinichi KANNO ,  Toshio FUJISAWA ,  Keisuke NAKATSUKA ,  Tomoya SANUKI

IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/02

Abstract: According to one embodiment, a storage device includes a stage on which a semiconductor wafer can be mounted, wherein data is capable of being read from the semiconductor wafer or data is capable of being written to the semiconductor wafer. The storage device further includes a plurality of probe pins for reading or writing data, and a controller connected the probe pins. The semiconductor wafer includes electrodes connectable to the probe pins, a first memory area that can store user data, and a second memory area that can store identification information for identification of the semiconductor wafer and a check code for checking integrity of the identification information. The controller is capable of reading the identification information and the check code from the second memory area.