公开(公告)号：US10038002B2

公开(公告)日：2018-07-31

申请号：US15296858

申请日：2016-10-18

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/10 ,  H01L29/51 ,  H01L21/311 ,  H01L21/28 ,  H01L21/285 ,  H01L27/1157

CPC classification number: H01L27/11556 ,  H01L21/31111 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/1037 ,  H01L29/40114 ,  H01L29/513 ,  H01L29/66825

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

公开(公告)号：US20180069015A1

公开(公告)日：2018-03-08

申请号：US15808468

申请日：2017-11-09

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Lijing Gou ,  Gordon Haller ,  Luan C. Tran

IPC: H01L27/11556 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L21/28035 ,  H01L21/28282 ,  H01L21/302 ,  H01L21/30625 ,  H01L21/31105 ,  H01L21/32055 ,  H01L27/11582

Abstract: Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate (SGD) transistor, the gate region at least partially surrounding the vertical channel; a dielectric barrier formed in the gate region; a first isolation layer formed above the gate region and the dielectric barrier; a drain region of the SGD transistor formed above the vertical channel; and a second isolation layer formed above the first isolation layer and the drain region, wherein the second isolation layer includes a conductive contact in electrical contact with the drain region of the SGD transistor. Additional apparatus and methods are disclosed.

公开(公告)号：US20150064871A1

公开(公告)日：2015-03-05

申请号：US14534454

申请日：2014-11-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： John Hopkins ,  James Matthew ,  Jie Sun ,  Gordon Haller

IPC: H01L21/762 ,  H01L27/115

CPC classification number: H01L21/76224 ,  H01L27/11524 ,  H01L27/1157

Abstract: An embodiment includes forming an isolation region between first and second active regions in a semiconductor, forming an opening between the first and second active regions by removing a portion of the isolation region, and forming a dielectric plug within the opening so that the dielectric plug is between the first and second active regions and so that a portion of the dielectric plug extends below upper surfaces of the first and second active regions. The dielectric plug may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.

Abstract translation: 一个实施例包括在半导体中在第一和第二有源区之间形成隔离区，通过去除隔离区的一部分形成第一和第二有源区之间的开口，以及在该开口内形成电介质塞， 在第一和第二有源区之间并且使得电介质塞的一部分延伸到第一和第二有源区的上表面之下。 电介质插塞可以由对于特定的各向同性的去除化学物质具有比隔离区域的电介质材料更低的去除速率的电介质材料形成。

公开(公告)号：US20210366931A1

公开(公告)日：2021-11-25

申请号：US17397338

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/10 ,  H01L29/51 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/66

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

公开(公告)号：US20200227427A1

公开(公告)日：2020-07-16

申请号：US16834291

申请日：2020-03-30

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

IPC: H01L27/11556 ,  H01L29/10 ,  H01L29/51 ,  H01L21/311 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/28 ,  H01L29/66

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

公开(公告)号：US09530683B2

公开(公告)日：2016-12-27

申请号：US14534454

申请日：2014-11-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： John Hopkins ,  James Matthew ,  Jie Sun ,  Gordon Haller

IPC: H01L21/336 ,  H01L21/762 ,  H01L27/115

CPC classification number: H01L21/76224 ,  H01L27/11524 ,  H01L27/1157

Abstract: An embodiment includes forming an isolation region between first and second active regions in a semiconductor, forming an opening between the first and second active regions by removing a portion of the isolation region, and forming a dielectric plug within the opening so that the dielectric plug is between the first and second active regions and so that a portion of the dielectric plug extends below upper surfaces of the first and second active regions. The dielectric plug may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.

Abstract translation: 一个实施例包括在半导体中在第一和第二有源区之间形成隔离区，通过去除隔离区的一部分形成第一和第二有源区之间的开口，以及在该开口内形成电介质塞， 在第一和第二有源区之间并且使得电介质塞的一部分延伸到第一和第二有源区的上表面之下。 电介质插塞可以由对于特定的各向同性的去除化学物质具有比隔离区域的电介质材料更低的去除速率的电介质材料形成。

公开(公告)号：US20140346613A1

公开(公告)日：2014-11-27

申请号：US14292443

申请日：2014-05-30

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Gordon Haller

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/785 ,  H01L21/3086 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

Abstract: There is provided fin methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins.

Abstract translation: 提供了用于制造翅片结构的翅片方法。 更具体地，翅片结构形成在基板中。 翅片结构可以包括由通道分开的两个翅片，其中翅片可以用作场效应晶体管的翅片。 翅片结构形成在衬底的上表面下方，并且可以在不利用光刻掩模来形成以蚀刻鳍片的情况下形成。

公开(公告)号：US20140239303A1

公开(公告)日：2014-08-28

申请号：US13774599

申请日：2013-02-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hongbin Zhu ,  Gordon Haller ,  Paul D. Long

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/823412 ,  H01L23/5226 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66787 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.

Abstract translation: 一些实施例包括具有堆叠结构的半导体器件，该堆叠结构包括形成在衬底上的多个交替层的介电材料和多晶硅。 这样的半导体器件还可以包括至少一个具有高纵横比并且延伸到堆叠结构中的开口至与衬底相邻的水平，形成在邻近衬底的开口下部的第一多晶硅沟道，第二聚硅 - 硅沟道，以及设置在开口中的第一多晶硅沟道和第二多晶硅沟道之间的WSiX材料。 WSiX材料与衬底相邻，并且可以用作蚀刻着色层和导电触点，以在开口中接触第一多晶硅沟道和第二多晶硅沟道。 其他实施例包括制造半导体器件的方法。

公开(公告)号：US08546215B2

公开(公告)日：2013-10-01

申请号：US13781862

申请日：2013-03-01

Applicant: Micron Technology, Inc.

Inventor： Gordon Haller ,  Sanh Dang Tang ,  Steve Cummings

IPC: H01L29/94

CPC classification number: H01L21/823487 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888

Abstract: A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.

公开(公告)号：US11177279B2

公开(公告)日：2021-11-16

申请号：US16876896

申请日：2020-05-18

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  Anilkumar Chandolu ,  Indra V. Chary ,  Darwin A. Clampitt ,  Gordon Haller ,  Thomas George ,  Brett D. Lowe ,  David A. Daycock

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11573

Abstract: In an example, a method of forming a stacked memory array includes forming a stack of alternating first and second dielectrics, forming a termination structure through the stack, the termination structure comprising a dielectric liner around a conductor, forming a set of contacts concurrently with forming the termination structure, forming a third dielectric over an upper surface of the stack and an upper surface of the termination structure, forming a first opening through the third dielectric and the stack between first and second groups of semiconductor structures so that the first opening exposes an upper surface of the conductor, and removing the conductor from the termination structure to form a second opening lined with the dielectric liner. In some examples, the dielectric liner can include a rectangular or a triangular tab or a pair of prongs that can have a rectangular profile or that can be tapered.