公开(公告)号：US20240071505A1

公开(公告)日：2024-02-29

申请号：US18237815

申请日：2023-08-24

Applicant: Micron Technology, Inc.

Inventor： Jiewei Chen ,  Mithun Kumar Ramasahayam ,  Tomoko Ogura Iwasaki ,  June Lee ,  Luyen Vu

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3459

Abstract: Control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel potential of each of the plurality of sub-blocks to a boost voltage. The control logic further selectively discharges the boost voltage from one or more of the plurality of sub-blocks according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. In addition, the control logic causes a single programming pulse to be applied to a selected wordline of the plurality of wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.

公开(公告)号：US20240029809A1

公开(公告)日：2024-01-25

申请号：US18376198

申请日：2023-10-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sheyang Ning ,  Lawrence Celso Miranda ,  Tomoko Ogura Iwasaki ,  Ting Luo ,  Luyen Vu

IPC: G11C29/42 ,  G11C29/44 ,  G11C7/10 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C29/4401 ,  G11C7/1096 ,  G11C7/1069 ,  G11C29/12005

Abstract: Apparatus might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the apparatus to apply a sense voltage level to a control gate of a memory cell of the array of memory cells, generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three, deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell, and deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell.

公开(公告)号：US08806155B2

公开(公告)日：2014-08-12

申请号：US13775645

申请日：2013-02-25

Applicant: Micron Technology, Inc.

Inventor： Luyen Vu ,  Uday Chandrasekhar ,  Dean Nobunaga

IPC: G06F13/00 ,  G06F3/06 ,  G06F12/08 ,  G06F13/10

CPC classification number: G06F3/0601 ,  G06F3/0628 ,  G06F3/0653 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0873 ,  G06F13/102 ,  G06F2212/214 ,  G06F2212/313 ,  Y02D10/13

Abstract: Memory devices and methods facilitate handling of data received by a memory device through the use of data grouping and assignment of data validity status values to grouped data. For example, data is received and delineated into one or more data groups and a data validity status is associated with each data group. Data groups having a valid status are latched into one or more cache registers for storage in an array of memory cells wherein data groups comprising an invalid status are rejected by the one or more cache registers.

Abstract translation: 存储器设备和方法通过使用数据分组和将数据有效性状态值分配给分组数据来促进对由存储器设备接收的数据的处理。 例如，数据被接收并被描绘成一个或多个数据组，并且数据有效性状态与每个数据组相关联。 具有有效状态的数据组被锁存到一个或多个高速缓存寄存器中以存储在存储器单元阵列中，其中包括无效状态的数据组被一个或多个高速缓存寄存器拒绝。

公开(公告)号：US20250069683A1

公开(公告)日：2025-02-27

申请号：US18782624

申请日：2024-07-24

Applicant: Micron Technology, Inc.

Inventor： Luyen Vu ,  Alex Sheng-Huang Lee ,  Wei Lic Chew

IPC: G11C29/00

Abstract: A memory device includes a memory array includes memory cells grouped into one or more address ranges. Control logic is coupled to the memory array and configured to detect one or more errors associated with one or more stored data items corresponding to a first address range of one or more address ranges. The control logic can determine that a number of the one or more stored data items exceeds a number of redundant memory locations for the first address space. Control logic can remap an association of a first memory address of at least one of the stored data items from a first address within the first address space to a second address in a second address range, where the second address range includes one or more available redundant memory locations.

公开(公告)号：US09431421B2

公开(公告)日：2016-08-30

申请号：US14850781

申请日：2015-09-10

Applicant: Micron Technology, Inc.

Inventor： Luyen Vu ,  Mark A. Helm

IPC: H01L27/115 ,  H01L29/16 ,  H01L29/04

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/04 ,  H01L29/16

Abstract: Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. Each of the different pillars in a respective one of the repeating pillar patterns is capable of being electrically coupled to a different data line of a plurality of data lines. Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern having at least portions of 7 different pillars. All 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD).

公开(公告)号：US20160005761A1

公开(公告)日：2016-01-07

申请号：US14850781

申请日：2015-09-10

Applicant: Micron Technology, Inc.

Inventor： Luyen Vu ,  Mark A. Helm

IPC: H01L27/115 ,  H01L29/04 ,  H01L29/16

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/04 ,  H01L29/16

Abstract: Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. Each of the different pillars in a respective one of the repeating pillar patterns is capable of being electrically coupled to a different data line of a plurality of data lines. Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern having at least portions of 7 different pillars. All 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD).

Abstract translation: 一些实施例包括具有基本上六边形最紧密堆积布置的半导体柱的装置。 六边形最紧密的包装布置包括具有7个不同支柱的至少部分的重复支柱图案。 重复柱图案中的相应一个中的每个不同的支柱能够电耦合到多条数据线的不同数据线。 一些实施例包括具有基本上六边形最紧密堆积布置的半导体柱的装置。 六边形最接近的包装布置包括具有7个不同柱的至少一部分的重复柱图形。 重复柱状图案的所有7个不同的柱由单个排水侧选择栅（SGD）包围。

公开(公告)号：US20230274786A1

公开(公告)日：2023-08-31

申请号：US17681976

申请日：2022-02-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sheyang Ning ,  Lawrence Celso Miranda ,  Tomoko Ogura Iwasaki ,  Ting Luo ,  Luyen Vu

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C7/10

CPC classification number: G11C29/42 ,  G11C29/4401 ,  G11C29/12005 ,  G11C7/1069 ,  G11C7/1096

Abstract: Apparatus might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the apparatus to apply a sense voltage level to a control gate of a memory cell of the array of memory cells, generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three, deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell, and deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell.

公开(公告)号：US10790029B2

公开(公告)日：2020-09-29

申请号：US16111319

申请日：2018-08-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luyen Vu ,  Kalyan C. Kavalipurau ,  Jae-Kwan Park ,  Erwin E. Yu

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C7/04 ,  G11C16/30 ,  G11C16/32 ,  G11C5/14

Abstract: Apparatus and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation.

公开(公告)号：US09159736B2

公开(公告)日：2015-10-13

申请号：US14175901

申请日：2014-02-07

Applicant: Micron Technology, Inc.

Inventor： Luyen Vu ,  Mark A. Helm

IPC: H01L27/115 ,  H01L29/16 ,  H01L29/04

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/04 ,  H01L29/16

Abstract: Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. Each of the different pillars in a respective one of the repeating pillar patterns is capable of being electrically coupled to a different data line of a plurality of data lines. Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern having at least portions of 7 different pillars. All 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD).

Abstract translation: 一些实施例包括具有基本上六边形最紧密堆积布置的半导体柱的装置。 六边形最紧密的包装布置包括具有7个不同支柱的至少部分的重复支柱图案。 重复柱图案中的相应一个中的每个不同的支柱能够电耦合到多条数据线的不同数据线。 一些实施例包括具有基本上六边形最紧密堆积布置的半导体柱的装置。 六边形最接近的包装布置包括具有7个不同柱的至少一部分的重复柱图形。 重复柱状图案的所有7个不同的柱由单个排水侧选择栅（SGD）包围。

公开(公告)号：US20140068186A1

公开(公告)日：2014-03-06

申请号：US13775645

申请日：2013-02-25

Applicant: Micron Technology, Inc.

Inventor： Luyen Vu ,  Uday Chandrasekhar ,  Dean Nobunaga

IPC: G06F12/08

CPC classification number: G06F3/0601 ,  G06F3/0628 ,  G06F3/0653 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0873 ,  G06F13/102 ,  G06F2212/214 ,  G06F2212/313 ,  Y02D10/13

Abstract: Memory devices and methods facilitate handling of data received by a memory device through the use of data grouping and assignment of data validity status values to grouped data. For example, data is received and delineated into one or more data groups and a data validity status is associated with each data group. Data groups having a valid status are latched into one or more cache registers for storage in an array of memory cells wherein data groups comprising an invalid status are rejected by the one or more cache registers.

Abstract translation: 存储器设备和方法通过使用数据分组和将数据有效性状态值分配给分组数据来促进对由存储器设备接收的数据的处理。 例如，数据被接收并被描绘成一个或多个数据组，并且数据有效性状态与每个数据组相关联。 具有有效状态的数据组被锁存到一个或多个高速缓存寄存器中以存储在存储器单元阵列中，其中包括无效状态的数据组被一个或多个高速缓存寄存器拒绝。