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    Memory device
    1.
    发明授权
    Memory device 有权

    公开(公告)号：US12274058B2

    公开(公告)日：2025-04-08

    申请号：US17699212

    申请日：2022-03-21

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shih-Hung Chen ,  Chun-Hsiung Hung

    IPC: H10B41/35 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B12/00 ,  H10B41/20 ,  H10B43/20 ,  H10B43/35

    Abstract: A memory device for artificial intelligence calculation includes a memory structure, a controller chip, and a processer chip. The memory structure includes a first memory chip, and a stack of second memory chips, in which a memory density of each of the second memory chips is greater than a memory density of the first memory chip. The controller chip is electrically connected to the first memory chip and the second memory chips. The processer chip is electrically connected to the controller chip.

    Classification model training using diverse training source and inference engine using same
    2.
    发明授权
    Classification model training using diverse training source and inference engine using same 有权

    公开(公告)号：US11775822B2

    公开(公告)日：2023-10-03

    申请号：US16885638

    申请日：2020-05-28

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shih-Hung Chen ,  Tzu-Hsiang Su

    IPC: G06N3/08 ,  G06N3/04

    CPC classification number: G06N3/08 ,  G06N3/04

    Abstract: A method for generating a classification model using a training data set. An iterative procedure for training an ANN model, in which an iteration includes selecting a small sample of training data from a source of training data, training the model using the sample, using the model in inference mode over a larger sample of the training data, and reviewing the results of the inferencing. The results can be evaluated to determine whether the model is satisfactory, and if it does not meet specified criteria, then cycles of sampling, training, inferencing and reviewing results (STIR cycles) are repeated in an iterative process until the criteria are met. A classification engine trained as described herein is provided.

    Memory device
    3.
    发明授权
    Memory device 有权

    公开(公告)号：US11289130B2

    公开(公告)日：2022-03-29

    申请号：US16997986

    申请日：2020-08-20

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shih-Hung Chen

    IPC: H01L23/538 ,  G11C5/06 ,  G11C5/02 ,  H01L25/065

    Abstract: A memory device includes a periphery wafer, a memory array chip stack, and a plurality of first conductive contacts. The periphery wafer has a functional surface. The memory array chip stack is disposed on the periphery wafer and has a functional surface, in which the functional surface of the periphery wafer faces toward the functional surface of the memory array chip stack, and a first side of the memory array chip stack is in a staircase configuration. The first conductive contacts are on the first side of the memory array chip stack, and between and interconnecting the functional surface of the periphery wafer and the functional surface of the memory array chip stack.

    CONNECTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME
    6.
    发明申请
    CONNECTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
    连接器结构及其制造方法

    公开(公告)号：US20170047245A1

    公开(公告)日：2017-02-16

    申请号：US14826257

    申请日：2015-08-14

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shih-Hung Chen

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

    CPC classification number: H01L21/76885 ,  H01L21/76834 ,  H01L27/11582 ,  H01L28/00

    Abstract: A connector structure for electrically contacting with a conductive layer disposed on a substrate is provided. The connector structure comprises a conductive connecting element disposed on the substrate. The conductive connecting element comprises a connecting part and an extending part. The connecting part has a bottom portion electrically contacting with the conductive layer. The extending part laterally extends outwards from a top portion of the connecting part, and the extending part and the connecting part are respectively formed of different materials.

    Abstract translation: 提供了一种用于与设置在基板上的导电层电接触的连接器结构。 连接器结构包括设置在基板上的导电连接元件。 导电连接元件包括连接部分和延伸部分。 连接部分具有与导电层电接触的底部部分。 延伸部分从连接部分的顶部向外侧向延伸，并且延伸部分和连接部分分别由不同的材料形成。

    Memory structure
    8.
    发明授权
    Memory structure 有权
    内存结构

    公开(公告)号：US09542979B1

    公开(公告)日：2017-01-10

    申请号：US14834475

    申请日：2015-08-25

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shih-Hung Chen

    IPC: G11C5/02 ,  G11C8/10 ,  G11C8/08

    CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10 ,  G11C16/10 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11565

    Abstract: A memory structure includes N array regions and N page buffers coupled to the N array regions, respectively. N is an integer ≧2. Each of the N array regions includes a 3D array of a plurality of memory cells. The memory cells have a lateral distance d between two adjacent memory cells on a horizontal cell plane of the 3D array. Each of the N array regions further includes a plurality of conductive lines. The conductive lines are disposed over and coupled to the 3D array. The conductive lines have a pitch p, and p/d=⅕ to ½. The N array regions and the N page buffers are arranged on one line along an extension direction of the conductive lines.

    Abstract translation: 存储器结构包括分别与N个阵列区域耦合的N个阵列区域和N个页面缓冲器。 N为整数≥2。 N个阵列区域中的每一个包括多个存储单元的3D阵列。 存储单元在3D阵列的水平单元平面上具有两个相邻存储单元之间的横向距离d。 N个阵列区域中的每一个还包括多条导线。 导线布置在3D阵列上并耦合到3D阵列。 导线具有间距p，p / d =⅕至½。 N个阵列区域和N个页面缓冲器沿着导电线的延伸方向布置在一条线上。

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