利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

33 条记录 (耗时 0.03 秒)

    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08716746B2

    公开(公告)日：2014-05-06

    申请号：US13205845

    申请日：2011-08-09

    申请人： Masaki Koyama ,  Yasushi Ookura ,  Akitaka Soeno ,  Tatsuji Nagaoka ,  Takahide Sugiyama ,  Sachiko Aoi ,  Hiroko Iguchi

    发明人： Masaki Koyama ,  Yasushi Ookura ,  Akitaka Soeno ,  Tatsuji Nagaoka ,  Takahide Sugiyama ,  Sachiko Aoi ,  Hiroko Iguchi

    IPC分类号： H01L29/66

    CPC分类号： H01L29/1095 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/8613

    摘要： In a semiconductor device, an IGBT cell includes a trench passing through a base layer of a semiconductor substrate to a drift layer of the semiconductor substrate, a gate insulating film on an inner surface of the trench, a gate electrode on the gate insulating film, a first conductivity-type emitter region in a surface portion of the base layer, and a second conductivity-type first contact region in the surface portion of the base layer. The IGBT cell further includes a first conductivity-type floating layer disposed within the base layer to separate the base layer into a first portion including the emitter region and the first contact region and a second portion adjacent to the drift layer, and an interlayer insulating film disposed to cover an end of the gate electrode. A diode cell includes a second conductivity-type second contact region in the surface portion of the base layer.

    摘要翻译： 在半导体装置中，IGBT单元包括通过半导体衬底的基底层到半导体衬底的漂移层的沟槽，沟槽内表面上的栅极绝缘膜，栅极绝缘膜上的栅电极， 在基底层的表面部分中的第一导电型发射极区域和在基底层的表面部分中的第二导电类型的第一接触区域。 IGBT单元还包括设置在基极层内的第一导电型浮动层，以将基极层分离成包括发射极区域和第一接触区域的第一部分和与漂移层相邻的第二部分，以及层间绝缘膜 设置成覆盖栅电极的端部。 二极管单元在基层的表面部分包括第二导电类型的第二接触区域。

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20120043581A1

    公开(公告)日：2012-02-23

    申请号：US13205845

    申请日：2011-08-09

    申请人： Masaki KOYAMA ,  Yasushi Ookura ,  Akitaka Soeno ,  Tatsuji Nagaoka ,  Takahide Sugiyama ,  Sachiko Aoi ,  Hiroko Iguchi

    发明人： Masaki KOYAMA ,  Yasushi Ookura ,  Akitaka Soeno ,  Tatsuji Nagaoka ,  Takahide Sugiyama ,  Sachiko Aoi ,  Hiroko Iguchi

    IPC分类号： H01L29/739

    CPC分类号： H01L29/1095 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/8613

    摘要： In a semiconductor device, an IGBT cell includes a trench passing through a base layer of a semiconductor substrate to a drift layer of the semiconductor substrate, a gate insulating film on an inner surface of the trench, a gate electrode on the gate insulating film, a first conductivity-type emitter region in a surface portion of the base layer, and a second conductivity-type first contact region in the surface portion of the base layer. The IGBT cell further includes a first conductivity-type floating layer disposed within the base layer to separate the base layer into a first portion including the emitter region and the first contact region and a second portion adjacent to the drift layer, and an interlayer insulating film disposed to cover an end of the gate electrode. A diode cell includes a second conductivity-type second contact region in the surface portion of the base layer.

    摘要翻译： 在半导体装置中，IGBT单元包括通过半导体衬底的基底层到半导体衬底的漂移层的沟槽，沟槽内表面上的栅极绝缘膜，栅极绝缘膜上的栅电极， 在基底层的表面部分中的第一导电型发射极区域和在基底层的表面部分中的第二导电类型的第一接触区域。 IGBT单元还包括设置在基极层内的第一导电型浮动层，以将基极层分离成包括发射极区域和第一接触区域的第一部分和与漂移层相邻的第二部分，以及层间绝缘膜 设置成覆盖栅电极的端部。 二极管单元在基层的表面部分包括第二导电类型的第二接触区域。

    Semiconductor device having semiconductor substrate including diode region and IGBT region
    4.
    发明授权
    Semiconductor device having semiconductor substrate including diode region and IGBT region 有权
    具有半导体衬底的半导体器件包括二极管区和IGBT区

    公开(公告)号：US08299496B2

    公开(公告)日：2012-10-30

    申请号：US13242960

    申请日：2011-09-23

    申请人： Tatsuji Nagaoka ,  Akitaka Soeno

    发明人： Tatsuji Nagaoka ,  Akitaka Soeno

    IPC分类号： H01L29/74 ,  H01L31/111

    CPC分类号： H01L21/761 ,  H01L27/0727 ,  H01L29/32 ,  H01L29/7397 ,  H01L29/861

    摘要： Provided is a semiconductor device including a semiconductor substrate in which a diode region and an IGBT region are formed. A separation region formed of a p-type semiconductor is formed in a range between the diode region and the IGBT region and extending from an upper surface of the semiconductor substrate to a position deeper than both a lower end of an anode region and a lower end of a body region. A diode lifetime control region is formed within a diode drift region. A carrier lifetime in the diode lifetime control region is shorter than that in the diode drift region outside the diode lifetime control region. An end of the diode lifetime control region on an IGBT region side is located right below the separation region.

    摘要翻译： 提供一种半导体器件，其包括其中形成二极管区域和IGBT区域的半导体衬底。 在二极管区域和IGBT区域之间的范围内形成由p型半导体形成的分离区域，并且从半导体衬底的上表面延伸到比阳极区域和下端部的下端更深的位置 的身体区域。 二极管寿命控制区形成在二极管漂移区内。 二极管寿命控制区域中的载流子寿命短于二极管寿命控制区域外的二极管漂移区域中的载流子寿命。 IGBT区域侧的二极管寿命控制区域的一端位于分离区域正下方。

    Method of forming gallium oxide film
    5.
    发明授权
    Method of forming gallium oxide film 有权

    公开(公告)号：US11515146B2

    公开(公告)日：2022-11-29

    申请号：US16697273

    申请日：2019-11-27

    申请人： Tatsuji Nagaoka ,  Hiroyuki Nishinaka ,  Masahiro Yoshimoto

    发明人： Tatsuji Nagaoka ,  Hiroyuki Nishinaka ,  Masahiro Yoshimoto

    IPC分类号： H01L21/02

    摘要： A method of forming a gallium oxide film is provided, and the method may include supplying mist of a material solution comprising gallium atoms and chlorine atoms to a surface of a substrate while heating the substrate so as to form the gallium oxide film on the surface of the substrate, in which a molar concentration of chlorine in the material solution is equal to or more than 3.0 times and equal to or less than 4.5 times a molar concentration of gallium in the material solution.

    MIS-TYPE SEMICONDUCTOR DEVICE
    7.
    发明申请
    MIS-TYPE SEMICONDUCTOR DEVICE 失效
    MIS型半导体器件

    公开(公告)号：US20060194392A1

    公开(公告)日：2006-08-31

    申请号：US11383097

    申请日：2006-05-12

    申请人： Tatsuji Nagaoka

    发明人： Tatsuji Nagaoka

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/7813 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A MIS-type semiconductor device has reduced ON-resistance by securing an overlapping area between the gate electrode and the drift region, and has low switching losses by reducing the feedback capacitance. The MIS-type semiconductor device includes a p-type base region, an n-type drift region, a p+-type stopper region in the base region, a gate insulation film on the base region, a gate electrode on the gate insulation film, an oxide film on the drift region, a field plate on the oxide film, and a source electrode. The position (P) of the impurity concentration peak in base region is located more closely to the drift region. The oxide film is thinner on the side of the gate electrode. The field plate is connected electrically to the source electrode, the spacing (dg) between the gate insulation film and the stopper region is 2.5 μm or narrower, and the minimum spacing (x) between the drain region and the stopper region is 5.6 μm or narrower. The minimum thickness of the oxide film is equal to or larger than the thickness of the gate insulation film and equal to or smaller than the ratio Vb/Ec of the breakdown voltage Vb to the critical dielectric breakdown strength of silicon Ec. The drift region can be formed of first and second drift regions, with the first drift region being more heavily doped. The gate electrode and the drift region can be buried.

    摘要翻译： MIS型半导体器件通过确保栅极电极和漂移区域之间的重叠区域而降低了导通电阻，并且通过减小反馈电容而具有低的开关损耗。 MIS型半导体器件包括基极区域中的p型基极区域，n型漂移区域，ap + + / - 型停止区域，基极区域上的栅极绝缘膜，栅极 栅绝缘膜上的电极，漂移区上的氧化膜，氧化膜上的场板和源电极。 碱性区域中的杂质浓度峰的位置（P）更靠近漂移区。 氧化膜在栅电极侧较薄。 场板与源电极电连接，栅绝缘膜与止挡区之间的间隔（dg）为2.5μm或更窄，漏区与阻挡区之间的最小间距（x）为5.6μm或 更窄 氧化膜的最小厚度等于或大于栅极绝缘膜的厚度，并且等于或小于击穿电压Vb与硅Ec的临界介电击穿强度的比率Vb / Ec。 漂移区可以由第一和第二漂移区形成，其中第一漂移区是更重掺杂的。 栅电极和漂移区可以埋入。

    MIS-type semiconductor device
    8.
    发明授权
    MIS-type semiconductor device 失效
    MIS型半导体器件

    公开(公告)号：US07067877B2

    公开(公告)日：2006-06-27

    申请号：US10781360

    申请日：2004-02-18

    申请人： Tatsuji Nagaoka

    发明人： Tatsuji Nagaoka

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/7393 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A MIS-type semiconductor device has reduced ON-resistance by securing an overlapping area between the gate electrode and the drift region, and has low switching losses by reducing the feedback capacitance. The MIS-type semiconductor device includes a p-type base region, an n-type drift region, a p+-type stopper region in the base region, a gate insulation film on the base region, a gate electrode on the gate insulation film, an oxide film on the drift region, a field plate on the oxide film, and a source electrode. The position (P) of the impurity concentration peak in base region is located more closely to the drift region. The oxide film is thinner on the side of the gate electrode. The field plate is connected electrically to the source electrode, the spacing (dg) between the gate insulation film and the stopper region is 2.5 μm or narrower, and the minimum spacing (x) between the drain region and the stopper region is 5.6 μm or narrower. The minimum thickness of the oxide film is equal to or larger than the thickness of the gate insulation film and equal to or smaller than the ratio Vb/Ec of the breakdown voltage Vb to the critical dielectric breakdown strength of silicon Ec. The drift region can be formed of first and second drift regions, with the first drift region being more heavily doped. The gate electrode and the drift region can be buried.

    摘要翻译： MIS型半导体器件通过确保栅极电极和漂移区域之间的重叠区域而降低了导通电阻，并且通过减小反馈电容而具有低的开关损耗。 MIS型半导体器件包括基极区域中的p型基极区域，n型漂移区域，ap + + / - 型停止区域，基极区域上的栅极绝缘膜，栅极 栅绝缘膜上的电极，漂移区上的氧化膜，氧化膜上的场板和源电极。 碱性区域中的杂质浓度峰的位置（P）更靠近漂移区。 氧化膜在栅电极侧较薄。 场板与源电极电连接，栅绝缘膜与止挡区之间的间隔（dg）为2.5μm或更窄，漏区与阻挡区之间的最小间距（x）为5.6μm或 更窄 氧化膜的最小厚度等于或大于栅极绝缘膜的厚度，并且等于或小于击穿电压Vb与硅Ec的临界介电击穿强度的比率Vb / Ec。 漂移区可以由第一和第二漂移区形成，其中第一漂移区是更重掺杂的。 栅电极和漂移区可以埋入。

    Super-junction semiconductor device and method of manufacturing the same
    10.
    发明授权
    Super-junction semiconductor device and method of manufacturing the same 有权
    超结半导体器件及其制造方法

    公开(公告)号：US07002205B2

    公开(公告)日：2006-02-21

    申请号：US10735501

    申请日：2003-12-12

    申请人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

    发明人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.

    摘要翻译： 公开了一种半导体器件，其使用其周边部分具有高于漏极漂移层中的击穿电压的击穿电压，而不采用保护环或场板。 优选实施例包括漏极漂移区，其具有由n个漂移电流通路区域和彼此交替布置的p个分隔区域形成的第一交变导电类型层，以及具有由n个区域和p形成的第二交变导电类型层的击穿承受区域 区域彼此交替布置，击穿承受区域在设备的接通状态下不提供电流路径，并且在器件的关断状态被耗尽。 由于耗尽层从多个pn结到两个方向扩展到设备的OFF状态的n个区域和p区域，所以p型基极区域的相邻区域，半导体芯片的外部区域和 半导体芯片耗尽。 因此，击穿耐受区域的击穿电压高于漏极漂移区域的击穿电压。