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公开(公告)号：US12283962B2
公开(公告)日：2025-04-22
申请号：US18239309
申请日：2023-08-29
Applicant: NXP B.V.
Inventor： Nenad Pavlovic , Chuang Lu , Vladislav Dyachenko
Abstract: A method of controlling a frequency-modulated oscillator 110 of a phase-locked loop circuit 100 is described, wherein the oscillator 110 comprises a bank of capacitors 413. The method comprises the steps of (i) switching a capacitor 414 of the bank of capacitors 413 to change an output frequency 1050 of an output signal 112 of the oscillator 110 from a first frequency 1051 to a second frequency 1052, (ii) determining a frequency information associated with the capacitor 414 and based on at least one of the first frequency 1051 and the second frequency 1052; and (iii) writing the frequency information to a look-up table 224, 225, 226 stored in a control unit 120 of the oscillator 110. A corresponding frequency-modulated oscillator 110 and phase-locked loop circuit 100 are also described.
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公开(公告)号：US20240080031A1
公开(公告)日：2024-03-07
申请号：US18239309
申请日：2023-08-29
Applicant: NXP B.V.
Inventor： Nenad Pavlovic , Chuang Lu , Vladislav Dyachenko
Abstract: A method of controlling a frequency-modulated oscillator 110 of a phase-locked loop circuit 100 is described, wherein the oscillator 110 comprises a bank of capacitors 413. The method comprises the steps of (i) switching a capacitor 414 of the bank of capacitors 413 to change an output frequency 1050 of an output signal 112 of the oscillator 110 from a first frequency 1051 to a second frequency 1052, (ii) determining a frequency information associated with the capacitor 414 and based on at least one of the first frequency 1051 and the second frequency 1052; and (iii) writing the frequency information to a look-up table 224, 225, 226 stored in a control unit 120 of the oscillator 110. A corresponding frequency-modulated oscillator 110 and phase-locked loop circuit 100 are also described.
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公开(公告)号：US10735012B2
公开(公告)日：2020-08-04
申请号：US15849683
申请日：2017-12-21
Applicant: NXP B.V.
Inventor： Nenad Pavlovic
Abstract: A digitally controlled oscillator comprising a filtering digital to analogue converter, DAC, component and a voltage controlled oscillator, VCO, component comprising at least one control terminal arranged to receive a control voltage output by the DAC component; wherein the DAC component comprises a voltage generation component arranged to generate the control voltage and at least one configurable capacitive load component to which the control voltage is applied such that a filtering bandwidth of the DAC component is configurable by way of the at least one configurable capacitive load component.
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公开(公告)号：US10581439B1
公开(公告)日：2020-03-03
申请号：US16457845
申请日：2019-06-28
Applicant: NXP B.V.
Inventor： Nenad Pavlovic , Vladislav Dyachenko
Abstract: Embodiments of a clock synchronization unit of an All Digital Phase-Locked Loop (ADPLL), a successive approximation register (SAR) Time-to-Digital Converter (TDC) of an ADPLL and a method for clock synchronization in an ADPLL are disclosed. In one embodiment, a clock synchronization unit of an ADPLL includes a two-flop synchronizer, a phase frequency detector (PFD) connected to the two-flop synchronizer, and a synchronization control circuit configured to control the two-flop synchronizer and the PFD to perform clock synchronization between a reference clock input signal and a divided clock input signal and to control the two-flop synchronizer and the PFD to replace a performance of the clock synchronization between the reference clock input signal and the divided clock input signal with a PFD operation. Other embodiments are also described.
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公开(公告)号：US09584177B2
公开(公告)日：2017-02-28
申请号：US15041217
申请日：2016-02-11
Applicant: NXP B.V.
Inventor： Nenad Pavlovic , Vladislav Dyachenko , Tarik Saric
IPC: H04L1/00 , H04B1/7073 , H03L7/197 , H04B1/69 , H03C3/09
CPC classification number: H04B1/7073 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0958 , H03C3/0991 , H03L7/1976 , H04B2001/6912 , H04B2201/7073
Abstract: A phase locked loop is disclosed having a frequency controlled oscillator, a feedback path, a time to digital converter and a memory. The frequency controlled oscillator comprises a first control input for varying the frequency of the output of the frequency controlled oscillator so as to track a reference frequency and a second control input for modulating the frequency of the output signal so as to produce a chirp. The feedback path is configured to provide an input signal to the time to digital converter, and comprises modulation cancelling module operable to remove the frequency modulation resulting from the second control input from the output signal. The memory stores second control input values that each correspond with a desired chirp frequency and which compensate for non-linearity in the response of the frequency controlled oscillator to the second control input. The phase locked loop is operable in a chirp mode, in which the second control input is produced by determining a value for the second control input corresponding with a desired chirp frequency based on the stored second control input values in the memory, and in which the phase locked loop is configured to determine the first control input based on the feedback path from which the modulation cancelling module has removed the frequency modulation resulting from the second control input.
Abstract translation: 公开了一种具有频率控制振荡器，反馈路径，时间到数字转换器和存储器的锁相环。 频率控制振荡器包括用于改变频率控制振荡器的输出频率以跟踪参考频率的第一控制输入和用于调制输出信号的频率以产生啁啾的第二控制输入。 反馈路径被配置为向时间到数字转换器提供输入信号，并且包括调制解除模块，其可操作以从输出信号中去除由第二控制输入产生的频率调制。 存储器存储每个对应于期望啁啾频率并且补偿频率控制振荡器对第二控制输入的响应中的非线性的第二控制输入值。 锁相环可以在啁啾模式下操作，其中通过基于存储器中存储的第二控制输入值确定与期望啁啾频率对应的第二控制输入的值来产生第二控制输入，其中， 锁相环被配置为基于调制消除模块从其中移除由第二控制输入产生的频率调制的反馈路径来确定第一控制输入。
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Patent Agency Ranking
公开(公告)号：US08922288B2
公开(公告)日：2014-12-30
申请号：US13774163
申请日：2013-02-22
Applicant: NXP B.V.
CPC classification number: H03L5/00 , H03B5/06 , H03B5/12 , H03B5/1212 , H03B5/124 , H03B5/36 , H03L3/00
Abstract: An oscillator circuit comprising first and second resonator terminals for connecting to respective terminals of a resonator. The oscillator circuit also comprises a first inverting amplifier connected between the first and second resonator terminals in a first mode of operation; and a back to back pair of second inverting amplifiers connected between the first and second resonator terminals in a second mode of operation. There is also provided a controller configured to compare an operational parameter of the oscillator circuit to a switchover threshold, and switch the oscillator circuit from the first mode of operation to the second mode of operation when the operational parameter exceeds the switchover threshold.
Abstract translation: 一种振荡器电路，包括用于连接到谐振器的各个端子的第一和第二谐振器端子。 振荡器电路还包括在第一操作模式下连接在第一和第二谐振器端子之间的第一反相放大器; 以及在第二操作模式下连接在第一和第二谐振器端子之间的背靠背对的第二反相放大器。 还提供了一种控制器，被配置为将振荡器电路的操作参数与切换阈值进行比较，并且当操作参数超过切换阈值时，将振荡器电路从第一操作模式切换到第二操作模式。
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公开(公告)号：US20140070897A1
公开(公告)日：2014-03-13
申请号：US13774163
申请日：2013-02-22
Applicant: NXP B.V.
IPC: H03L5/00
CPC classification number: H03L5/00 , H03B5/06 , H03B5/12 , H03B5/1212 , H03B5/124 , H03B5/36 , H03L3/00
Abstract: An oscillator circuit (702; 802) comprising first and second resonator terminals (710, 712; 810, 812) for connecting to respective terminals of a resonator (704; 804). The oscillator circuit also comprises a first inverting amplifier (706; 806) connected between the first and second resonator terminals (710, 712; 810, 812) in a first mode of operation; and a back to back pair of second inverting amplifiers (706, 708; 806, 808) connected between the first and second resonator terminals (710, 712; 810, 812) in a second mode of operation. There is also provided a controller configured to compare an operational parameter of the oscillator circuit (702; 802) to a switchover threshold, and switch the oscillator circuit (702; 802) from the first mode of operation to the second mode of operation when the operational parameter exceeds the switchover threshold.
Abstract translation: 振荡器电路（702; 802）包括用于连接到谐振器（704,804）的相应端子的第一和第二谐振器端子（710,712; 810,812）。 振荡器电路还包括在第一操作模式下连接在第一和第二谐振器端子（710,712; 810,812）之间的第一反相放大器（706; 806） 以及在第二操作模式下连接在第一和第二谐振器端子（710,712; 810,812）之间的背靠背对的第二反相放大器（706,708,806,808）。 还提供了一种控制器，其被配置为将振荡器电路（702; 802）的操作参数与切换阈值进行比较，并且当振荡器电路（702; 802）从第一操作模式切换到第二操作模式时 操作参数超出切换阈值。
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公开(公告)号：US09496889B2
公开(公告)日：2016-11-15
申请号：US14512923
申请日：2014-10-13
Applicant: NXP B.V.
Inventor： Nenad Pavlovic
CPC classification number: H03M3/322 , H03M1/06 , H03M3/368 , H03M3/40 , H03M3/422 , H03M3/454 , H03M3/464 , H03M3/486 , H03M3/494 , H04B1/0003
Abstract: A sigma delta receiver achieves increased stability and noise reduction. The sigma delta receiver includes a first integrator stage, an isolation stage, a second integrator stage, and a quantization stage. The first integrator stage receives an analog radio frequency (RF) signal from an antenna and generates an analog baseband signal based on the analog RF signal. The isolation stage is coupled to an output of the first integrator stage. The isolation stage receives the analog baseband signal from the first integrator stage and amplifies the analog baseband signal. The second integrator stage is coupled to an output of the isolation stage to receive the analog baseband signal. The second integrator stage further amplifies the analog baseband signal. The quantization stage converts the analog baseband signal to a digital signal, and outputs the digital signal.
Abstract translation: Σ-Δ接收器实现了增加的稳定性和降噪。 Σ-Δ接收机包括第一积分器级，隔离级，第二积分级和量化级。 第一个积分器级从天线接收模拟射频（RF）信号，并根据模拟RF信号产生模拟基带信号。 隔离级耦合到第一积分器级的输出端。 隔离级接收来自第一积分器级的模拟基带信号，并放大模拟基带信号。 第二积分器级耦合到隔离级的输出端以接收模拟基带信号。 第二个积分器级进一步放大模拟基带信号。 量化级将模拟基带信号转换为数字信号，并输出数字信号。
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公开(公告)号：US10826387B2
公开(公告)日：2020-11-03
申请号：US16201088
申请日：2018-11-27
Applicant: NXP B.V.
Inventor： Vladislav Dyachenko , Nenad Pavlovic
Abstract: Embodiments of a method for operating a charge pump and a charge pump are disclosed. In an embodiment, a method for operating a charge pump involves during a first operating phase of the charge pump, setting a first current source of the charge pump according to a second current source of the charge pump, and, during a second operating phase of the charge pump that is subsequent to the first operating phase, providing current from the first current source to a load of the charge pump.
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公开(公告)号：US10191453B2
公开(公告)日：2019-01-29
申请号：US15041202
申请日：2016-02-11
Applicant: NXP B.V.
Inventor： Nenad Pavlovic , Vladislav Dyachenko , Tarik Saric
IPC: G04F10/00 , H03C3/09 , H03L7/197 , H03L7/085 , H03L7/099 , H03M1/38 , G01S7/02 , G01S7/35 , G01S13/32 , G01S13/00
Abstract: A time to digital converter may include a synchronization block configured to output a voltage pulse with duration based on a time difference between a reference oscillating signal and an input oscillating signal; a charge pump arranged to receive the voltage pulse and to convert the voltage pulse into a current pulse; an integrator comprising an integrator capacitor, the integrator being configured to receive the current pulse and integrate the current pulse as a charge on the integrator capacitor, resulting in an integrator output voltage; and a successive approximation register configured to determine the integrator output voltage with respect to a reference voltage by adjusting the charge on the integrator capacitor so as to reduce the integrator output voltage to within a least significant bit (D0) of a reference voltage by successive approximation, and configured to output the determined integrator output voltage as a digital signal.
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