Method for glob top encapsulation using molding tape with elevated sidewall

    公开(公告)号:US11637024B2

    公开(公告)日:2023-04-25

    申请号:US17072569

    申请日:2020-10-16

    Applicant: NXP B.V.

    Abstract: A lead frame used to assemble a semiconductor device, such as a smart card, has a first major surface including exposed leads and a second major surface including a die receiving area and one or more connection pads surrounding the die receiving area. The connection pads enable electrical connection of an Integrated Circuit (IC) die to the exposed leads. A molding tape sized and shaped like the lead frame is adhered to and covers the second major surface of the lead frame. The molding tape has a die receiving area cut-out that exposes the die receiving area and the connection pads on the second major surface of the lead frame and forms a cavity for receiving an encapsulant. The cut-out has an elevated sidewall for retaining the encapsulant within the cavity.

    Conductive trace design for smart card

    公开(公告)号:US10763203B1

    公开(公告)日:2020-09-01

    申请号:US16270607

    申请日:2019-02-08

    Applicant: NXP B.V.

    Abstract: A lead frame for assembling a smart card is formed with a substrate having first and second opposing major surfaces. A die receiving area is formed in the first major surface of the substrate and surrounded by conductive vias. A conductive coating is formed on the second major surface of the substrate and patterned to form electrical contact pads over the conductive vias. A conductive trace is formed on the first major surface of the substrate. The conductive trace extends between at least two adjacent vias and partially surrounds the at least two adjacent conductive vias, thereby forming a gap in the portion of the trace that surrounds the vias. An electrical connection between an integrated circuit chip and the conductive via extends over the gap. The gap prevents the electrical connection from inadvertently contacting the conductive trace.

    LEAD FRAME WITH PLATED LEAD TIPS
    3.
    发明申请

    公开(公告)号:US20190229044A1

    公开(公告)日:2019-07-25

    申请号:US15878292

    申请日:2018-01-23

    Applicant: NXP B.V.

    Abstract: A lead frame is formed with exposed lead tips. The leads are not attached at their tips to any of a tie bar, a dam bar or an end bar, so when the lead frame is plated, the lead tips are plated. During packaging, after die attach and molding, when the lead frame is cut from the frame assembly, the lead tips are not cut, so the plating remains on the tips. This improves solder joint reliability when the package is mounted on a PCB. The lead frame has connection bars that run parallel to the leads from the tie bar to the end bar. The connection bars provide stability to the leads during wire bonding, but are cut from the lead frame after wire bonding.

    REDUCING LEAD STRESS IN MICRO-ELECTRONIC PACKAGES
    4.
    发明申请
    REDUCING LEAD STRESS IN MICRO-ELECTRONIC PACKAGES 审中-公开
    降低微电子封装中的引线应力

    公开(公告)号:US20170047275A1

    公开(公告)日:2017-02-16

    申请号:US14823486

    申请日:2015-08-11

    Applicant: NXP B.V.

    Inventor: Wiwat Tanwongwan

    Abstract: Consistent with an example embodiment, there is a semiconductor device that comprises a lead frame assembly having a non-conductive material (NCM) sheet placed on a location of the lead frame assembly. A device die having a length, width, and thickness, is attached to the NCM sheet, the device die being attached to the NCM with an adhesive. The NCM sheet has a length and width greater than the length and width of the device die and the NCM sheet has a thickness less than the thickness of the device die. The NCM sheet mitigates wire bond lifting at device die bond pads by reducing bouncing of the wire bond leads owing to stress and movement of the lead frame assembly underneath the device die.

    Abstract translation: 与示例性实施例一致,存在一种半导体器件,其包括具有放置在引线框组件的位置上的非导电材料(NCM)片的引线框架组件。 具有长度,宽度和厚度的器件模具连接到NCM片材上,器件裸片用粘合剂附着到NCM上。 NCM片材的长度和宽度大于器件裸片的长度和宽度,NCM片材的厚度小于器件裸片的厚度。 NCM板材通过减少引线框架组件在器件裸片下方的应力和运动来减少引线接合引线的跳动,从而减少器件管芯接合焊盘处的引线接合提升。

    Electronic device, device package, and method of fabrication

    公开(公告)号:US11114239B2

    公开(公告)日:2021-09-07

    申请号:US16689347

    申请日:2019-11-20

    Applicant: NXP B.V.

    Abstract: A device includes a leadframe and an electronic component. The leadframe includes a first leadframe element having a first surface and a second leadframe element adjacent to the first leadframe element, the first and second leadframe elements being separate from one another, the second leadframe element having a second surface. A first flange extends from a first outer edge of the first leadframe element and extends away from the first surface of the first leadframe element. A second flange extends from a second outer edge of the second leadframe element and extends away from the second surface of the second leadframe element. The electronic component is coupled to the first and second surfaces of the first and second leadframe elements such that the first and second flanges are located at opposing first and second sidewalls of the electronic component.

    ELECTRONIC DEVICE, DEVICE PACKAGE, AND METHOD OF FABRICATION

    公开(公告)号:US20210151251A1

    公开(公告)日:2021-05-20

    申请号:US16689347

    申请日:2019-11-20

    Applicant: NXP B.V.

    Abstract: A device includes a leadframe and an electronic component. The leadframe includes a first leadframe element having a first surface and a second leadframe element adjacent to the first leadframe element, the first and second leadframe elements being separate from one another, the second leadframe element having a second surface. A first flange extends from a first outer edge of the first leadframe element and extends away from the first surface of the first leadframe element. A second flange extends from a second outer edge of the second leadframe element and extends away from the second surface of the second leadframe element. The electronic component is coupled to the first and second surfaces of the first and second leadframe elements such that the first and second flanges are located at opposing first and second sidewalls of the electronic component.

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