公开(公告)号：US20150171160A1

公开(公告)日：2015-06-18

申请号：US14636311

申请日：2015-03-03

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki KAWASHIMA ,  Koichi TOBA ,  Yasushi ISHII ,  Toshikazu MATSUI ,  Takashi HASHIMOTO

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/60 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11573 ,  H01L28/40

Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.

公开(公告)号：US20130285057A1

公开(公告)日：2013-10-31

申请号：US13924175

申请日：2013-06-21

Applicant: Renesas Electronics Corporation

Inventor： Yasushi ISHII

IPC: H01L23/00

CPC classification number: H01L24/06 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Increase in the chip size of a semiconductor device is suppressed. The semiconductor device includes: circuit vias provided in an interlayer insulating film between upper and lower wiring layers and coupling these wiring layers together; a planar ring-shaped protecting via that is provided in the interlayer insulating film under an electrode pad and one side of which is coupled with the electrode pad; a protecting wiring layer comprised of a wiring layer coupled only with the other side of the protecting via; and a semiconductor element provided over the principal surface of a semiconductor substrate under the protecting wiring layer. The lower part of the electrode pad whose surface is exposed is encircled with the protecting via and the protecting wiring layer. The width of the protecting via is equal to or larger than the width of each circuit via.

公开(公告)号：US20190386013A1

公开(公告)日：2019-12-19

申请号：US16552524

申请日：2019-08-27

Applicant: Renesas Electronics Corporation

Inventor： Tsutomu OKAZAKI ,  Akira KATO ,  Kan YASUI ,  Kyoya NITTA ,  Digh HISAMOTO ,  Yasushi ISHII ,  Daisuke OKADA ,  Toshihiro TANAKA ,  Toshikazu MATSUI

IPC: H01L27/1157 ,  H01L29/51 ,  H01L29/06 ,  H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L27/11568 ,  H01L27/115 ,  H01L27/02 ,  G11C16/04 ,  H01L21/28 ,  H01L27/105

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

公开(公告)号：US20190096896A1

公开(公告)日：2019-03-28

申请号：US16200756

申请日：2018-11-27

Applicant: Renesas Electronics Corporation

Inventor： Tsutomu OKAZAKI ,  Daisuke OKADA ,  Kyoya NITTA ,  Toshihiro TANAKA ,  Akira KATO ,  Toshikazu MATSUI ,  Yasushi ISHII ,  Digh HISAMOTO ,  Kan YASUI

IPC: H01L27/1157 ,  H01L27/105 ,  H01L29/423 ,  H01L29/51 ,  H01L29/06 ,  H01L27/115 ,  H01L27/02 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11568 ,  G11C16/04

CPC classification number: H01L27/1157 ,  G11C16/0425 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

公开(公告)号：US20160190350A1

公开(公告)日：2016-06-30

申请号：US15062160

申请日：2016-03-06

Applicant: Renesas Electronics Corporation

Inventor： Kota FUNAYAMA ,  Hiraku CHAKIHARA ,  Yasushi ISHII

IPC: H01L29/792 ,  H01L27/115 ,  H01L23/535 ,  H01L23/532 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L23/53214 ,  H01L23/53257 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0653 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.

Abstract translation: 在存储单元（MC）的馈电区域中，在存储单元（MC）的馈电区域中，通过自对准在存储器nMIS（Qnm）的选择栅极（CG）的侧表面上提供存储器nMIS（Qnm）的侧壁形状的存储栅极（MG） 通过绝缘膜选择nMIS（Qnc），向存储栅电极（MG）提供电压的插头（PM）嵌入在形成在存储栅上的层间绝缘膜（9）中形成的接触孔（CM） 电极（MG）并且电连接到存储栅电极（MG）。 由于在选择栅电极（CG）的上表面上形成帽绝缘膜（CAP），所以可以防止插头（PM）与选择栅电极（CG）之间的导电。

公开(公告)号：US20150162284A1

公开(公告)日：2015-06-11

申请号：US14626331

申请日：2015-02-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasushi ISHII

IPC: H01L23/00 ,  H01L23/58

CPC classification number: H01L23/564 ,  H01L23/562 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05556 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/351 ,  H01L2924/00

Abstract: To improve reliability of a semiconductor device obtained through a dicing step. In a ring region, a first outer ring is provided outside a seal ring, and a second outer ring is provided outside the first outer ring. This can prevent a crack from reaching even the seal ring that exists in the ring region, for example, when a scribe region located outside the ring region is cut off by a dicing blade.

Abstract translation: 为了提高通过切割步骤获得的半导体器件的可靠性。 在环形区域中，第一外圈设置在密封环的外侧，第二外圈设置在第一外圈的外侧。 这可以防止裂纹甚至达到存在于环形区域中的密封环，例如当位于环形区域外侧的划线区域被切割刀片切断时。

公开(公告)号：US20140374816A1

公开(公告)日：2014-12-25

申请号：US14479362

申请日：2014-09-07

Applicant: Renesas Electronics Corporation

Inventor： Kota FUNAYAMA ,  Hiraku CHAKIHARA ,  Yasushi ISHII

IPC: H01L29/792 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L23/53214 ,  H01L23/53257 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0653 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.

Abstract translation: 在存储单元（MC）的馈电区域中，在存储单元（MC）的馈电区域中，通过自对准在存储器nMIS（Qnm）的选择栅极（CG）的侧表面上提供存储器nMIS（Qnm）的侧壁形状的存储栅极（MG） 通过绝缘膜选择nMIS（Qnc），向存储栅电极（MG）提供电压的插头（PM）嵌入在形成在存储栅上的层间绝缘膜（9）中形成的接触孔（CM） 电极（MG）并且电连接到存储栅电极（MG）。 由于在选择栅电极（CG）的上表面上形成帽绝缘膜（CAP），所以可以防止插头（PM）与选择栅电极（CG）之间的导电。

公开(公告)号：US20140209996A1

公开(公告)日：2014-07-31

申请号：US14242500

申请日：2014-04-01

Applicant: Renesas Electronics Corporation

Inventor： Koichi TOBA ,  Yasushi ISHII ,  Hiraku CHAKIHARA ,  Kota FUNAYAMA ,  Yoshiyuki KAWASHIMA ,  Takashi HASHIMOTO

IPC: H01L29/792

CPC classification number: H01L27/11568 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/792

Abstract: A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.

Abstract translation: 提供了具有非易失性存储器的半导体器件，其具有改进的特性。 半导体器件包括控制栅极电极，与控制栅电极相邻设置的存储栅电极，第一绝缘膜和包括电荷存储部分的第二绝缘膜。 在这些部件中，存储栅电极由包括位于第二绝缘膜上的第一硅区的硅膜和位于第一硅区之上的第二硅区构成。 第二硅区域含有p型杂质，第一硅区域的p型杂质浓度低于第二硅区域的p型杂质浓度。

公开(公告)号：US20160372537A1

公开(公告)日：2016-12-22

申请号：US15256285

申请日：2016-09-02

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki KAWASHIMA ,  Koichi TOBA ,  Yasushi ISHII ,  Toshikazu MATSUI ,  Takashi HASHIMOTO

IPC: H01L49/02 ,  H01L27/115 ,  H01L27/06

CPC classification number: H01L28/60 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11573 ,  H01L28/40

Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.

公开(公告)号：US20150137215A1

公开(公告)日：2015-05-21

申请号：US14609659

申请日：2015-01-30

Applicant: Renesas Electronics Corporation

Inventor： Tsutomu OKAZAKI ,  Daisuke OKADA ,  Kyoya NITTA ,  Toshihiro TANAKA ,  Akira KATO ,  Toshikazu MATSUI ,  Yasushi ISHII ,  Digh HISAMOTO ,  Kan YASUI

IPC: H01L27/115

CPC classification number: H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

Abstract translation: 半导体存储器阵列包括具有第一电荷存储层和第一非易失性存储单元的第一非易失性存储单元，第一非易失性存储单元与第一存储单元相邻，具有第二电荷存储层和第二栅电极 。 第一电极和第二电极在垂直于第一方向的第二方向上延伸，第一电极具有在第一方向上朝向第二电极延伸的第一接触部分，并且第二电极具有朝向第一电极的第二接触部分 第一个方向 第一和第二接触位置分别沿第二方向移动，第一电极和第一接触部分与第二电极和第二接触部分电气分离。