公开(公告)号：US10115652B2

公开(公告)日：2018-10-30

申请号：US15430455

申请日：2017-02-11

Applicant: Renesas Electronics Corporation

Inventor： Hideo Numabe ,  Koji Tateno ,  Yusuke Ojima ,  Yoshihiko Yokoi ,  Shinya Ishida ,  Hitoshi Matsuura

IPC: H01L27/06 ,  H01L23/34 ,  H01L21/265 ,  H01L21/285 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L49/02 ,  H01L29/06 ,  H03K17/16 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L29/861 ,  H03K17/08

Abstract: A semiconductor device includes a power device and a temperature detection diode. The semiconductor device has a device structure configured to insulate between a power lien of the power device and the temperature detection diode.

公开(公告)号：US10074744B2

公开(公告)日：2018-09-11

申请号：US15625771

申请日：2017-06-16

Applicant: Renesas Electronics Corporation

Inventor： Hideo Numabe ,  Nobuyuki Shirai ,  Hirokazu Kato ,  Tomoaki Uno ,  Kazuyuki Umezu

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L29/417 ,  H01L29/10 ,  H01L23/535

CPC classification number: H01L29/7813 ,  H01L23/535 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1033 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/32225

Abstract: A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.

公开(公告)号：US20170288053A1

公开(公告)日：2017-10-05

申请号：US15625771

申请日：2017-06-16

Applicant: Renesas Electronics Corporation

Inventor： Hideo Numabe ,  Nobuyuki Shirai ,  Hirokazu Kato ,  Tomoaki Uno ,  Kazuyuki Umezu

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L23/535 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L23/535 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1033 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.

公开(公告)号：US09711637B2

公开(公告)日：2017-07-18

申请号：US14406991

申请日：2014-01-31

Applicant: Renesas Electronics Corporation

Inventor： Hideo Numabe ,  Nobuyuki Shirai ,  Hirokazu Kato ,  Tomoaki Uno ,  Kazuyuki Umezu

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L23/535 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L23/535 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1033 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.