公开(公告)号：US09620182B2

公开(公告)日：2017-04-11

申请号：US14145116

申请日：2013-12-31

Applicant: SanDisk Technologies LLC

Inventor： Daniel Tuers ,  Abhijeet Manohar ,  Yoav Weinberg ,  Milton Lourenco Barrocas

IPC: G06F13/372 ,  G11C7/22 ,  G11C16/32 ,  G06F13/362 ,  G06F13/38 ,  G06F13/16

CPC classification number: G06F13/1689 ,  G06F13/1668 ,  G06F13/362 ,  G06F13/385 ,  G06F13/4068 ,  G11C7/22 ,  G11C16/32

Abstract: In a memory system where multiple memory chips communicate their ready/busy status on a shared bus line, a pulse mechanism is used for the individual memory chips to indicate their ready/busy status to the controller. In one example, the controller assigns pulse durations of differing lengths to the memory dies to allow the controller to distinguish between them. Techniques for dealing with bus collisions between the pulses of different chips are also described.

公开(公告)号：US10241704B2

公开(公告)日：2019-03-26

申请号：US15664536

申请日：2017-07-31

Applicant: SanDisk Technologies LLC

Inventor： Daniel Tuers ,  Abhijeet Manohar ,  Jonathan Hsu

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/14 ,  G06F11/10 ,  G11C29/00 ,  G11C16/34 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  G11C16/10 ,  G11C29/04

Abstract: A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.

公开(公告)号：US09978456B2

公开(公告)日：2018-05-22

申请号：US14543660

申请日：2014-11-17

Applicant: SanDisk Technologies LLC

Inventor： Anubhav Khandelwal ,  Dana Lee ,  Abhijeet Manohar ,  Henry Chin ,  Gautam Dusija ,  Daniel Tuers ,  Chris Avila ,  Cynthia Hsu

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3418

Abstract: Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for data read. In both cases, non-selected word lines that are unwritten or, in the case of finding the last written word line, may be unwritten are biased with a lower read-pass voltage then is typically used. The result of such reads can also be applied to an algorithm for finding the last written word by skipping a varying number of word lines. Performance in a last written page determination can also be improved by use of shorter bit line settling times than for a standard read.

公开(公告)号：US20170329549A1

公开(公告)日：2017-11-16

申请号：US15664536

申请日：2017-07-31

Applicant: SanDisk Technologies LLC

Inventor： Daniel Tuers ,  Abhijeet Manohar ,  Jonathan Hsu

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/00 ,  G11C29/52 ,  G11C29/44 ,  G11C29/42 ,  G06F12/14 ,  G11C16/34 ,  G11C29/04 ,  G11C16/10

CPC classification number: G06F3/0629 ,  G06F3/0619 ,  G06F3/0623 ,  G06F3/0679 ,  G06F11/1004 ,  G06F11/1012 ,  G06F12/1408 ,  G06F2212/402 ,  G11C16/10 ,  G11C16/3418 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  G11C29/70 ,  G11C29/82 ,  G11C2029/0409

Abstract: A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.

公开(公告)号：US10592122B2

公开(公告)日：2020-03-17

申请号：US14675261

申请日：2015-03-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Abhijeet Manohar ,  Daniel Tuers ,  Sathyanarayanan Subramanian ,  Judah Gamliel Hahn

IPC: G06F3/06

Abstract: A memory system may use adaptive trimming to control throughput and traffic from the host to/from the memory. The trimming parameters of memory may be adaptively changed based on the data rate from the host. The programming speed may be slowed in order to reduce wear and improve endurance. In particular, the data rate for the transfer of data from a data buffer to the memory (e.g. NAND flash) may be matched to the host data rate. This programming speed reduction may be triggered upon prediction of idle times in the host bus.

公开(公告)号：US09940271B2

公开(公告)日：2018-04-10

申请号：US15483695

申请日：2017-04-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Tuers ,  Abhijeet Manohar ,  Yoav Weinberg ,  Milton Lourenco Barrocas

IPC: G06F13/372 ,  G06F13/16 ,  G06F13/40 ,  G06F13/362 ,  G06F13/38

CPC classification number: G06F13/1689 ,  G06F13/1668 ,  G06F13/362 ,  G06F13/385 ,  G06F13/4068 ,  G11C7/22 ,  G11C16/32

Abstract: In a memory system where multiple memory chips communicate their ready/busy status on a shared bus line, a pulse mechanism is used for the individual memory chips to indicate their ready/busy status to the controller. In one example, the controller assigns pulse durations of differing lengths to the memory dies to allow the controller to distinguish between them. Techniques for dealing with bus collisions between the pulses of different chips are also described.

公开(公告)号：US20170212849A1

公开(公告)日：2017-07-27

申请号：US15483695

申请日：2017-04-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Daniel Tuers ,  Abhijeet Manohar ,  Yoav Weinberg ,  Milton Lourenco Barrocas

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1689 ,  G06F13/1668 ,  G06F13/362 ,  G06F13/385 ,  G06F13/4068 ,  G11C7/22 ,  G11C16/32

Abstract: In a memory system where multiple memory chips communicate their ready/busy status on a shared bus line, a pulse mechanism is used for the individual memory chips to indicate their ready/busy status to the controller. In one example, the controller assigns pulse durations of differing lengths to the memory dies to allow the controller to distinguish between them. Techniques for dealing with bus collisions between the pulses of different chips are also described.

公开(公告)号：US09558847B2

公开(公告)日：2017-01-31

申请号：US14550290

申请日：2014-11-21

Applicant: SanDisk Technologies LLC

Inventor： Daniel Tuers ,  Abhijeet Manohar

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/42 ,  G11C29/44 ,  G11C16/00

CPC classification number: G11C29/38 ,  G11C16/00 ,  G11C29/42 ,  G11C29/44

Abstract: A method of operating a nonvolatile memory block includes reading data from physical units in the block and determining individual error rates for data from the physical units. The error rate data is stored. This is repeated over multiple iterations and aggregated stored error rates are used to identify bad physical units in the block.

Abstract translation: 一种操作非易失性存储块的方法包括从块中的物理单元读取数据，并确定来自物理单元的数据的单独错误率。 存储错误率数据。 这是通过多次迭代重复的，聚合存储的错误率用于识别块中的不良物理单元。