公开(公告)号：US11424207B1

公开(公告)日：2022-08-23

申请号：US17246472

申请日：2021-04-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shiqian Shao ,  Fumiaki Toyama

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  H01L25/065

Abstract: To overcome a shortage of area for horizontal metal lines to connect word line switch transistors to corresponding word lines and for pass through signal lines, it is proposed to implement multiple architectures for the word line hook up regions. For example, some areas of a die will be designed to provide extra horizontal metal lines to connect word line switch transistors to word lines and other areas of the die will be designed to provide extra pass through signal lines.

公开(公告)号：US20220319603A1

公开(公告)日：2022-10-06

申请号：US17246469

申请日：2021-04-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shiqian Shao ,  Fumiaki Toyama

IPC: G11C16/08 ,  H01L25/065 ,  H01L23/00 ,  G11C16/04 ,  G11C16/34 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: To overcome a shortage of area for horizontal metal lines to connect word line switch transistors to corresponding word lines and for pass through signal lines, it is proposed to implement multiple architectures for the word line hook up regions. For example, some areas of a die will be designed to provide extra horizontal metal lines to connect word line switch transistors to word lines and other areas of the die will be designed to provide extra pass through signal lines.

公开(公告)号：US20230207504A1

公开(公告)日：2023-06-29

申请号：US17560610

申请日：2021-12-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shiqian Shao ,  Fumiaki Toyama ,  Tuan Pham

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: An integrated memory assembly comprises a control die bonded to a memory die. The memory die includes multiple non-volatile memory structures (e.g., planes, arrays, groups of blocks, etc.), each comprising a stack of alternating conductive and dielectric layers forming staircases at one or more edges of the non-volatile memory structures. The non-volatile memory structures are positioned with gaps between the non-volatile memory structures such that the gaps separate the staircases of adjacent non-volatile memory structures. Metal interlayer segments positioned in the gaps are connected to a top metal layer positioned above non-volatile memory structures and to one or more electrical circuits on the control die via zero, one or more other metal layers/segments.

公开(公告)号：US20230386576A1

公开(公告)日：2023-11-30

申请号：US17825337

申请日：2022-05-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shiqian Shao ,  Tuan Pham ,  Fumiaki Toyama

IPC: G11C16/04 ,  H01L27/11519 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/14

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/14

Abstract: A non-volatile memory apparatus comprises a stack of integrated memory assemblies. Each integrated memory assembly includes a memory die bonded to a control die and a set of power pads connected to metal lines in the respective memory die and control die. The memory dies comprise a non-volatile memory structure and a top metal layer for transmitting power signals above the memory structure. The control dies comprise a substrate, a control circuit positioned on the substrate for performing memory operations on a corresponding memory structure and a set of metals layers above the control circuit. The substrate comprises a set of conductive vias through the substrate that connect at one end to the top metal layer of the memory die of an adjacent integrated memory assembly and connect at a second end to the set of metals layers above the control circuit for routing signals between integrated memory assemblies.

公开(公告)号：US11728305B2

公开(公告)日：2023-08-15

申请号：US17317442

申请日：2021-05-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shiqian Shao ,  Fumiaki Toyama ,  Peter Rabkin

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L49/02 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L28/60 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19041 ,  H01L2924/19104

Abstract: A semiconductor structure includes a bonded assembly of a first semiconductor die including first metal bonding pads and a second semiconductor die including second metal bonding pads, and a capacitor structure including a first electrode, a second electrode, and a node dielectric. The first electrode includes first bonded pairs of metal bonding pads. The second electrode includes second bonded pairs of metal bonding pads. The node dielectric includes portions dielectric material layers laterally surrounding the metal bonding pads.

公开(公告)号：US11973044B2

公开(公告)日：2024-04-30

申请号：US17560610

申请日：2021-12-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shiqian Shao ,  Fumiaki Toyama ,  Tuan Pham

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: An integrated memory assembly comprises a control die bonded to a memory die. The memory die includes multiple non-volatile memory structures (e.g., planes, arrays, groups of blocks, etc.), each comprising a stack of alternating conductive and dielectric layers forming staircases at one or more edges of the non-volatile memory structures. The non-volatile memory structures are positioned with gaps between the non-volatile memory structures such that the gaps separate the staircases of adjacent non-volatile memory structures. Metal interlayer segments positioned in the gaps are connected to a top metal layer positioned above non-volatile memory structures and to one or more electrical circuits on the control die via zero, one or more other metal layers/segments.

公开(公告)号：US11894056B2

公开(公告)日：2024-02-06

申请号：US17677907

申请日：2022-02-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shiqian Shao ,  Fumiaki Toyama

IPC: G11C16/08 ,  G11C16/10 ,  H01L23/00 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  H01L24/14 ,  H01L2224/17104

Abstract: A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells, where X>Y.

公开(公告)号：US11817150B2

公开(公告)日：2023-11-14

申请号：US17246469

申请日：2021-04-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shiqian Shao ,  Fumiaki Toyama

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C11/56 ,  G11C16/34 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/08 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3459 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/1431 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/14511

Abstract: To overcome a shortage of area for horizontal metal lines to connect word line switch transistors to corresponding word lines and for pass through signal lines, it is proposed to implement multiple architectures for the word line hook up regions. For example, some areas of a die will be designed to provide extra horizontal metal lines to connect word line switch transistors to word lines and other areas of the die will be designed to provide extra pass through signal lines.

公开(公告)号：US20230268001A1

公开(公告)日：2023-08-24

申请号：US17677907

申请日：2022-02-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shiqian Shao ,  Fumiaki Toyama

IPC: G11C16/08 ,  G11C16/10 ,  G11C16/04 ,  H01L23/00

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  H01L24/14 ,  H01L2224/17104

Abstract: A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells, where X>Y.

公开(公告)号：US11139237B2

公开(公告)日：2021-10-05

申请号：US16547971

申请日：2019-08-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shiqian Shao ,  Jee-Yeon Kim ,  Fumiaki Toyama ,  Hirofumi Tokita

IPC: H01L27/115 ,  H01L23/522 ,  G11C5/06 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524

Abstract: A method of forming a three-dimensional memory device includes forming a vertically alternating sequence of insulating layers and spacer material layers over a substrate, where the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers, forming multiple sets of stepped surfaces in terrace regions of the vertically alternating sequence, forming memory stack structures through memory array regions of the vertically alternating sequence, and forming a metal interconnect structure which electrically connects a portion of a topmost electrically conductive layer in the first memory array region and a portion of a topmost electrically conductive layer in the second memory array region, and which extends above a horizontal plane of the topmost electrically conductive layer in the first memory array region and a portion of a topmost electrically conductive layer in the second memory array region.