公开(公告)号：US09401328B2

公开(公告)日：2016-07-26

申请号：US14865261

申请日：2015-09-25

Applicant: STMicroelectronics S.r.l.

Inventor： Andrea Paleari ,  Lorenzo Gola ,  Federica Ronchi ,  Sonia Pirotta

IPC: H01L23/52 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L21/288 ,  H01L21/285

CPC classification number: H01L23/53238 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/2885 ,  H01L21/76804 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electric contact structure includes a first structural layer; a second structural layer made of dielectric material extending over the first structural layer; and an intermediate layer made of conductive material extending between the first structural layer and the second structural layer. A trench extends in the second structural layer delimited laterally by a wall of the second structural layer and at the bottom by a surface region of the intermediate layer. A diffusion barrier extends in the trench covering the surface region of the intermediate layer and the wall of the second structural layer. The diffusion barrier is a TiW—TiN—TiW tri-layer.

Abstract translation: 电接触结构包括第一结构层; 由在第一结构层上延伸的介电材料制成的第二结构层; 以及在第一结构层和第二结构层之间延伸的由导电材料制成的中间层。 沟槽在第二结构层中延伸，第二结构层由第二结构层的壁横向限定，底部由中间层的表面区域延伸。 扩散屏障在覆盖中间层的表面区域和第二结构层的壁的沟槽中延伸。 扩散阻挡层是TiW-TiN-TiW三层。

公开(公告)号：US10483220B2

公开(公告)日：2019-11-19

申请号：US15239545

申请日：2016-08-17

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Andrea Paleari ,  Antonella Milani ,  Lucrezia Guarino ,  Federica Ronchi

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/525 ,  H01L23/528 ,  H01L23/532

Abstract: In one embodiment, a method manufactures a semiconductor device including metallizations having peripheral portions with one or more underlying layers having marginal regions extending facing the peripheral portions. The method includes: providing a sacrificial layer to cover the marginal regions of the underlying layer, providing the metallizations while the marginal regions of the underlying layer are covered by the sacrificial layer, and removing the sacrificial layer so that the marginal regions of the underlying layer extend facing the peripheral portions in the absence of contact interface therebetween, thereby avoiding thermo-mechanical stresses.

公开(公告)号：US20170221840A1

公开(公告)日：2017-08-03

申请号：US15239545

申请日：2016-08-17

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Andrea Paleari ,  Antonella Milani ,  Lucrezia Guarino ,  Federica Ronchi

IPC: H01L23/00

Abstract: In one embodiment, a method manufactures a semiconductor device including metallizations having peripheral portions with one or more underlying layers having marginal regions extending facing the peripheral portions. The method includes: providing a sacrificial layer to cover the marginal regions of the underlying layer, providing the metallizations while the marginal regions of the underlying layer are covered by the sacrificial layer, and removing the sacrificial layer so that the marginal regions of the underlying layer extend facing the peripheral portions in the absence of contact interface therebetween, thereby avoiding thermo-mechanical stresses.

公开(公告)号：US20150140767A1

公开(公告)日：2015-05-21

申请号：US14606165

申请日：2015-01-27

Applicant: STMicroelectronics S.r.l.

Inventor： Giuseppe Croce ,  Paolo Gattari ,  Andrea Paleari ,  Alessandro Dundulachi

IPC: H01L29/66

CPC classification number: H01L29/66659 ,  H01L29/42368 ,  H01L29/7835

Abstract: A MOS transistor for power applications is formed in a substrate of semiconductor material by a method integrated in a process for manufacturing integrated circuits which uses an STI technique for forming insulating regions. The method includes the phases of forming an insulating element on a top surface of the substrate and forming a control electrode on a free surface of the insulating element. The insulating element insulates the control electrode from the substrate. The insulating element includes a first portion and a second portion. The extension of the first portion along a first direction perpendicular to the top surface is lower than the extension of the second portion along such first direction. The phase of forming the insulating element includes generating the second portion by locally oxidizing the top surface.

Abstract translation: 用于功率应用的MOS晶体管通过集成在用于形成绝缘区域的STI技术的集成电路的制造工艺中的方法形成在半导体材料的衬底中。 该方法包括在基板的顶表面上形成绝缘元件并在绝缘元件的自由表面上形成控制电极的阶段。 绝缘元件使控制电极与衬底绝缘。 绝缘元件包括第一部分和第二部分。 第一部分沿着垂直于顶面的第一方向的延伸比沿第一方向的第二部分的延伸小。 形成绝缘元件的相包括通过局部氧化顶表面来产生第二部分。

公开(公告)号：US09960131B2

公开(公告)日：2018-05-01

申请号：US15251355

申请日：2016-08-30

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Paolo Colpani ,  Antonella Milani ,  Lucrezia Guarino ,  Andrea Paleari

IPC: H01L21/44 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L23/50 ,  H01L23/522 ,  H01L23/562 ,  H01L24/00 ,  H01L24/03 ,  H01L2224/02205 ,  H01L2224/02215 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05562 ,  H01L2224/05655 ,  H01L2924/04642 ,  H01L2924/05042 ,  H01L2924/351

Abstract: In one embodiment, a semiconductor device includes one or more metallizations, such as, e.g., Cu-RDL metallizations, provided on a passivation layer over a dielectric layer. A via is provided through the passivation layer and the dielectric layer in the vicinity of the corners of the metallization. The via may be a “dummy” via without electrical connections to an active device and may be provided at a distance between approximately 1 micron (10−6 m.) and approximately 10 micron (10−5 m.) from each one of said converging sides landing on an underlying metal layer.

公开(公告)号：US20170221841A1

公开(公告)日：2017-08-03

申请号：US15251355

申请日：2016-08-30

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Paolo Colpani ,  Antonella Milani ,  Lucrezia Guarino ,  Andrea Paleari

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L23/50 ,  H01L23/522 ,  H01L23/562 ,  H01L24/00 ,  H01L24/03 ,  H01L2224/02205 ,  H01L2224/02215 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05562 ,  H01L2224/05655 ,  H01L2924/04642 ,  H01L2924/05042 ,  H01L2924/351

Abstract: In one embodiment, a semiconductor device includes one or more metallizations, such as, e.g., Cu-RDL metallizations, provided on a passivation layer over a dielectric layer. A via is provided through the passivation layer and the dielectric layer in the vicinity of the corners of the metallization. The via may be a “dummy” via without electrical connections to an active device and may be provided at a distance between approximately 1 micron (10−6 m.) and approximately 10 micron (10−5 m.) from each one of said converging sides landing on an underlying metal layer.

公开(公告)号：US20150008519A1

公开(公告)日：2015-01-08

申请号：US14492243

申请日：2014-09-22

Applicant: STMicroelectronics S.r.l.

Inventor： Simone Dario Mariana ,  Andrea Paleari ,  Stephane Wen Yung Bach ,  Paolo Gattari

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/7823 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

Abstract: According to a process for manufacturing an integrated power device, projections and depressions are formed in a semiconductor body that extend in a first direction and are arranged alternated in succession in a second direction, transversely to the first direction. Further provided are a first conduction region and a second conduction region. The first conduction region and the second conduction region define a current flow direction parallel to the first direction, along the projections and the depressions. To form the projections and the depressions, portions of the semiconductor body that extend in the first direction and correspond to the depressions, are selectively oxidized.

Abstract translation: 根据用于制造集成电力装置的方法，在半导体本体中形成有沿第一方向延伸并且沿与第一方向横向的第二方向相继交替设置的凹凸。 还提供了第一导电区域和第二导电区域。 第一导电区域和第二导电区域沿着突起和凹陷限定平行于第一方向的电流流动方向。 为了形成突起和凹陷，半导体本体的沿第一方向延伸并对应于凹陷的部分被选择性地氧化。

公开(公告)号：US09299610B2

公开(公告)日：2016-03-29

申请号：US14714738

申请日：2015-05-18

Applicant: STMicroelectronics S.r.l.

Inventor： Andrea Paleari ,  Giuseppe Croce

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/10 ,  H01L21/74 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L21/76895 ,  H01L21/743 ,  H01L21/76897 ,  H01L21/823418 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/66477 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7825

Abstract: A MOS transistor includes a semiconductor layer with a drain region and a body region. A first insulating layer is disposed over the semiconductor layer, a gate-precursor layer is disposed over the first insulating layer, a second insulating layer disposed over the first insulating layer and a third insulating layer disposed over the second insulating layer. A source opening extends through the third insulating layer, the second insulating layer, the gate-precursor layer, and the first insulating layer. An implant through the source opening forms a source-precursor region in the semiconductor layer. The source opening is then lined and an body contact opening is made through the liner, the source-precursor region and into the body region. An implant through the body contact opening forms the body contact region below the source-precursor. The body contact opening is then filled with a metal.

Abstract translation: MOS晶体管包括具有漏极区域和体区域的半导体层。 第一绝缘层设置在半导体层之上，栅极前体层设置在第一绝缘层之上，第二绝缘层设置在第一绝缘层上，第三绝缘层设置在第二绝缘层上。 源极开口延伸穿过第三绝缘层，第二绝缘层，栅极 - 前体层和第一绝缘层。 通过源极开口的植入物在半导体层中形成源极 - 前体区域。 然后排出源开口，并且通过衬垫，源 - 前体区域并进入体区域中制造体接触开口。 通过身体接触开口的植入物形成源 - 前体下方的身体接触区域。 然后用金属填充身体接触开口。

公开(公告)号：US20150255341A1

公开(公告)日：2015-09-10

申请号：US14714738

申请日：2015-05-18

Applicant: STMicroelectronics S.r.l.

Inventor： Andrea Paleari ,  Giuseppe Croce

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L21/76895 ,  H01L21/743 ,  H01L21/76897 ,  H01L21/823418 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/66477 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7825

Abstract: A MOS transistor includes a semiconductor layer with a drain region and a body region. A first insulating layer is disposed over the semiconductor layer, a gate-precursor layer is disposed over the first insulating layer, a second insulating layer disposed over the first insulating layer and a third insulating layer disposed over the second insulating layer. A source opening extends through the third insulating layer, the second insulating layer, the gate-precursor layer, and the first insulating layer. An implant through the source opening forms a source-precursor region in the semiconductor layer. The source opening is then lined and an body contact opening is made through the liner, the source-precursor region and into the body region. An implant through the body contact opening forms the body contact region below the source-precursor. The body contact opening is then filled with a metal.

Abstract translation: MOS晶体管包括具有漏极区域和体区域的半导体层。 第一绝缘层设置在半导体层之上，栅极前体层设置在第一绝缘层之上，第二绝缘层设置在第一绝缘层上，第三绝缘层设置在第二绝缘层上。 源极开口延伸穿过第三绝缘层，第二绝缘层，栅极 - 前体层和第一绝缘层。 通过源极开口的植入物在半导体层中形成源极 - 前体区域。 然后排出源开口，并且通过衬垫，源 - 前体区域并进入体区域中制造体接触开口。 通过身体接触开口的植入物形成源 - 前体下方的身体接触区域。 然后用金属填充身体接触开口。