公开(公告)号：US09306029B2

公开(公告)日：2016-04-05

申请号：US14150264

申请日：2014-01-08

Applicant: STMicroelectronics S.r.l.

Inventor： Leonardo Fragapane ,  Antonino Alessandria

IPC: H01L29/43 ,  H01L29/66 ,  H01L29/423 ,  H01L29/739

CPC classification number: H01L29/4236 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7827

Abstract: A device includes an epitaxial region extending into a front surface of a chip. A portion of the chip adjacent the epitaxial region defines a collector. A gate is provided in a trench extending into the epitaxial region from the front surface. An emitter includes a body extending into the epitaxial region at a first side of the trench and a source extending into the body region from the front surface at the trench. A dummy emitter extends into the epitaxial region from the front surface at a second side of the trench opposite said first side. The dummy emitter lacks the source. The gate extends along a first wall of the trench facing the emitter region. A dummy gate is formed in the trench in a manner electrically isolated from the gate and extending along a second wall of the trench opposite said first wall.

Abstract translation: 一种器件包括延伸到芯片前表面的外延区域。 与外延区域相邻的芯片的一部分限定了集电极。 栅极设置在从前表面延伸到外延区域的沟槽中。 发射器包括在沟槽的第一侧延伸到外延区域中的主体和从沟槽的前表面延伸到主体区域中的源极。 虚拟发射器在与第一侧相对的沟槽的第二侧处从前表面延伸到外延区域中。 虚拟发射器缺乏源。 栅极沿面向发射极区域的沟槽的第一壁延伸。 在沟槽中以与栅极电隔离并沿着与第一壁相对的沟槽的第二壁延伸的方式形成虚拟栅极。

公开(公告)号：US09564541B2

公开(公告)日：2017-02-07

申请号：US14943794

申请日：2015-11-17

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Antonino Alessandria ,  Leonardo Fragapane

IPC: H01L29/66 ,  H01L29/868 ,  H01L29/78 ,  H01L27/06 ,  H01L27/07 ,  H01L27/08 ,  H01L29/06 ,  H01L29/36 ,  H01L29/43

CPC classification number: H01L29/868 ,  H01L27/0629 ,  H01L27/0664 ,  H01L27/0694 ,  H01L27/0727 ,  H01L27/0814 ,  H01L29/0692 ,  H01L29/36 ,  H01L29/43 ,  H01L29/66136 ,  H01L29/7804

Abstract: A diode is integrated on a semiconductor chip having anode and cathode surfaces opposite to each other. The diode comprises a cathode region extending inwardly from the cathode surface, a drift region extending between the anode surface and the cathode region, and a plurality of anode regions extending from the anode surface in the drift region. The diode further comprises a cathode electrode coupled with the cathode region, and an anode electrode that contacts one or more contacted anode regions of said anode regions and is electrically insulated from one or more floating anode regions of the anode regions. The diode is configured so that charge carriers are injected from the floating anode regions into the drift region in response to applying of a control voltage exceeding a threshold voltage.

Abstract translation: 二极管集成在具有彼此相对的阳极和阴极表面的半导体芯片上。 二极管包括从阴极表面向内延伸的阴极区域，在阳极表面和阴极区域之间延伸的漂移区域以及从漂移区域中的阳极表面延伸的多个阳极区域。 二极管还包括与阴极区域耦合的阴极电极和接触所述阳极区域的一个或多个接触阳极区域并与阳极区域的一个或多个浮动阳极区域电绝缘的阳极电极。 二极管被配置为使得电荷载流子响应于施加超过阈值电压的控制电压而从浮置阳极区域注入漂移区域。

公开(公告)号：US20160071984A1

公开(公告)日：2016-03-10

申请号：US14943794

申请日：2015-11-17

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Antonino Alessandria ,  Leonardo Fragapane

IPC: H01L29/868 ,  H01L29/66 ,  H01L29/06 ,  H01L27/06 ,  H01L29/36 ,  H01L29/43

CPC classification number: H01L29/868 ,  H01L27/0629 ,  H01L27/0664 ,  H01L27/0694 ,  H01L27/0727 ,  H01L27/0814 ,  H01L29/0692 ,  H01L29/36 ,  H01L29/43 ,  H01L29/66136 ,  H01L29/7804

Abstract: A diode is integrated on a semiconductor chip having anode and cathode surfaces opposite to each other. The diode comprises a cathode region extending inwardly from the cathode surface, a drift region extending between the anode surface and the cathode region, and a plurality of anode regions extending from the anode surface in the drift region. The diode further comprises a cathode electrode coupled with the cathode region, and an anode electrode that contacts one or more contacted anode regions of said anode regions and is electrically insulated from one or more floating anode regions of the anode regions. The diode is configured so that charge carriers are injected from the floating anode regions into the drift region in response to applying of a control voltage exceeding a threshold voltage.

公开(公告)号：US20150280015A1

公开(公告)日：2015-10-01

申请号：US14656331

申请日：2015-03-12

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Leonardo Fragapane ,  Antonino Alessandria

IPC: H01L29/868 ,  H01L29/66

CPC classification number: H01L29/868 ,  H01L27/0629 ,  H01L27/0664 ,  H01L27/0694 ,  H01L27/0727 ,  H01L27/0814 ,  H01L29/0692 ,  H01L29/36 ,  H01L29/43 ,  H01L29/66136 ,  H01L29/7804

Abstract: A diode is integrated on a semiconductor chip having anode and cathode surfaces opposite to each other. The diode comprises a cathode region extending inwardly from the cathode surface, a drift region extending between the anode surface and the cathode region, and a plurality of anode regions extending from the anode surface in the drift region. The diode further comprises a cathode electrode coupled with the cathode region, and an anode electrode that contacts one or more contacted anode regions of said anode regions and is electrically insulated from one or more floating anode regions of the anode regions. The diode is configured so that charge carriers are injected from the floating anode regions into the drift region in response to applying of a control voltage exceeding a threshold voltage.

Abstract translation: 二极管集成在具有彼此相对的阳极和阴极表面的半导体芯片上。 二极管包括从阴极表面向内延伸的阴极区域，在阳极表面和阴极区域之间延伸的漂移区域以及从漂移区域中的阳极表面延伸的多个阳极区域。 二极管还包括与阴极区域耦合的阴极电极和接触所述阳极区域的一个或多个接触阳极区域并与阳极区域的一个或多个浮动阳极区域电绝缘的阳极电极。 二极管被配置为使得电荷载流子响应于施加超过阈值电压的控制电压而从浮置阳极区域注入漂移区域。

公开(公告)号：US11854809B2

公开(公告)日：2023-12-26

申请号：US18061795

申请日：2022-12-05

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Edoardo Zanetti ,  Simone Rascuna' ,  Mario Giuseppe Saggio ,  Alfio Guarnera ,  Leonardo Fragapane ,  Cristina Tringali

IPC: H01L21/04 ,  H01L21/285 ,  H01L29/872 ,  H01L29/66 ,  H01L29/16 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/046 ,  H01L21/0495 ,  H01L21/28537 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

公开(公告)号：US11545362B2

公开(公告)日：2023-01-03

申请号：US17244393

申请日：2021-04-29

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Edoardo Zanetti ,  Simone Rascuna' ,  Mario Giuseppe Saggio ,  Alfio Guarnera ,  Leonardo Fragapane ,  Cristina Tringali

IPC: H01L29/16 ,  H01L21/04 ,  H01L21/285 ,  H01L29/872 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

公开(公告)号：US09520468B2

公开(公告)日：2016-12-13

申请号：US14166075

申请日：2014-01-28

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Angelo Magri′ ,  Antonino Sebastiano Alessandria ,  Stefania Fortuna ,  Leonardo Fragapane

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/1037 ,  H01L29/405 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: A power device integrated on a semiconductor substrate and having a plurality of conductive bridges within a trench gate structure. In an embodiment, a semiconductor substrate includes a trench having sidewalls and a bottom, the walls and bottom are covered with a first insulating coating layer which then also includes a conductive gate structure. An embodiment provides the formation of the conductive gate structure with covering at least the sidewalls with a second conductive coating layer of a first conductive material. This results in a conductive central region of a second conductive material having a different resistivity than the first conductive material forming a plurality of conductive bridges between said second conductive coating layer and said conductive central region.

Abstract translation: 集成在半导体衬底上并在沟槽栅极结构内具有多个导电桥的功率器件。 在一个实施例中，半导体衬底包括具有侧壁和底部的沟槽，壁和底部被第一绝缘涂层覆盖，然后第一绝缘涂层还包括导电栅极结构。 一个实施例提供形成导电栅极结构，至少用第一导电材料的第二导电涂层覆盖侧壁。 这导致第二导电材料的导电中心区域具有与第一导电材料不同的电阻率，该第一导电材料在所述第二导电涂层和所述导电中心区域之间形成多个导电桥。

公开(公告)号：US09515136B2

公开(公告)日：2016-12-06

申请号：US14666013

申请日：2015-03-23

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Leonardo Fragapane

IPC: H01L29/15 ,  H01L31/0312 ,  H01L29/06 ,  H01L29/16 ,  H01L21/761 ,  H01L21/266 ,  H01L21/82 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L21/0415 ,  H01L21/266 ,  H01L21/761 ,  H01L21/8213 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/7393 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/8611

Abstract: An integrated device has: a structural layer of semiconductor material doped with a first conductivity type and having a top surface defining a plane; a functional region, doped with a second conductivity type, arranged in an active area of the structural layer at the top surface, in the proximity of an edge area of the integrated device, which externally surrounds the active area; and an edge termination region, doped with the second conductivity type, joined to the functional region and arranged in the edge area. The edge termination region has a doping profile and a junction depth that vary in a first direction parallel to the plane.

Abstract translation: 集成器件具有：掺杂有第一导电类型且具有限定平面的顶表面的半导体材料的结构层; 掺杂有第二导电类型的功能区域，其布置在所述结构层的顶表面的有源区域中，所述功能区域在所述集成器件的边缘区域附近，所述边缘区域在外部围绕所述有源区域; 并且掺杂有第二导电类型的边缘终止区域连接到功能区域并且布置在边缘区域中。 边缘终端区域具有在平行于平面的第一方向上变化的掺杂分布和结深度。

公开(公告)号：US09461130B2

公开(公告)日：2016-10-04

申请号：US14972794

申请日：2015-12-17

Applicant: STMicroelectronics S.r.l.

Inventor： Leonardo Fragapane ,  Antonino Alessandria

IPC: H01L21/332 ,  H01L29/423 ,  H01L29/739 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/4236 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7827

Abstract: A device includes an epitaxial region extending into a front surface of a chip. A portion of the chip adjacent the epitaxial region defines a collector. A gate is provided in a trench extending into the epitaxial region from the front surface. An emitter includes a body extending into the epitaxial region at a first side of the trench and a source extending into the body region from the front surface at the trench. A dummy emitter extends into the epitaxial region from the front surface at a second side of the trench opposite said first side. The dummy emitter lacks the source. The gate extends along a first wall of the trench facing the emitter region. A dummy gate is formed in the trench in a manner electrically isolated from the gate and extending along a second wall of the trench opposite said first wall.

公开(公告)号：US11018008B2

公开(公告)日：2021-05-25

申请号：US16209680

申请日：2018-12-04

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Edoardo Zanetti ,  Simone Rascuná ,  Mario Giuseppe Saggio ,  Alfio Guarnera ,  Leonardo Fragapane ,  Cristina Tringali

IPC: H01L21/04 ,  H01L21/285 ,  H01L29/872 ,  H01L29/66 ,  H01L29/16 ,  H01L29/78 ,  H01L29/06

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.