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    Storage device and operating method of storage controller
    1.
    发明授权
    Storage device and operating method of storage controller 有权

    公开(公告)号：US12189980B2

    公开(公告)日：2025-01-07

    申请号：US18136041

    申请日：2023-04-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eun Chu Oh ,  Beomkyu Shin

    IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

    Abstract: The present disclosure provides storage devices and methods for operating the same. In some embodiments, a storage device includes a non-volatile memory including a plurality of sub-blocks that are independently erasable, and a processor configured to control a garbage collection operation on the plurality of sub-blocks. The plurality of sub-blocks includes a plurality of first sub-blocks that have a first block size and a plurality of second sub-blocks that have a second block size. The second block size is different from the first block size. The processor is further configured to select a victim sub-block with a lowest ratio of a valid page count to an invalid page count from among the plurality of sub-blocks, and copy a valid page of the victim sub-block to a target sub-block from among the plurality of sub-blocks.

    MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD OF MEMORY SYSTEM
    2.
    发明公开
    MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD OF MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240264934A1

    公开(公告)日：2024-08-08

    申请号：US18426975

    申请日：2024-01-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jungho PARK ,  Insu kim ,  Beomkyu Shin ,  Jaeyong Jeong

    IPC: G06F12/02 ,  G06F12/0882 ,  G06F13/16

    CPC classification number: G06F12/0246 ,  G06F12/0882 ,  G06F13/1668 ,  G06F2212/7201

    Abstract: In some embodiments, the memory system for communicating with a host includes a non-volatile memory device storing first mapping information, a volatile memory device storing second mapping information, and a memory controller. The first mapping information indicates a relationship between a logical address and a portion of a first physical address. The first physical address indicates a location where user data is stored. The second mapping information indicates a second relationship between the logical address and a second physical address that corresponds to a remaining portion of the first physical address. The memory controller is configured to obtain a target logical address that has been received from the host, and determine, based on the second mapping information, a target second physical address mapped to the target logical address. The non-volatile memory device is configured to obtain a target first physical address by using the first mapping information.

    Storage device, operation method of storage device, and storage system using the same
    5.
    发明授权
    Storage device, operation method of storage device, and storage system using the same 有权

    公开(公告)号：US12260116B2

    公开(公告)日：2025-03-25

    申请号：US18492762

    申请日：2023-10-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Wonseb Jeong ,  Yang Seok Ki ,  Jungmin Seo ,  Beomkyu Shin ,  Sangoak Woo ,  Younggeon Yoo ,  Chanho Yoon ,  Myungjune Jung

    IPC: G06F3/06 ,  G06F12/0802

    Abstract: A storage device includes a nonvolatile memory device and a storage controller. The storage controller includes a multi-protocol host interface circuit that receives a first-type request including a first logical address from an external host and transmits/receives data corresponding to the first-type request with the external host by a block unit. Additionally, the multi-protocol host interface circuit receives a second-type request including a first physical address from the external host and transmits/receives data corresponding to the second-type request with the external host by a unit smaller than the block unit. A mapping cache manager manages an address translation table cache, sends an address translation request including the first physical address to the external host, and receives a response including mapping information corresponding to the first physical address from the external host.

    Non-volatile memory device, controller and memory system
    7.
    发明授权
    Non-volatile memory device, controller and memory system 有权

    公开(公告)号：US11763869B2

    公开(公告)日：2023-09-19

    申请号：US17549095

    申请日：2021-12-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kuiyon Mun ,  Beomkyu Shin ,  Jaeyong Jeong

    IPC: G11C8/18 ,  G11C8/06 ,  G11C7/22 ,  G11C7/10

    CPC classification number: G11C8/18 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/06

    Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a clock pin, a clock signal being received from a controller through the clock pin; a first input/output pin; a second input/output pin, data being received from the controller in synchronization with the clock signal through the second input/output pin; a command/address buffer configured to operate at a first operating speed and buffer a command and an address received through the first input/output pin in synchronization with the clock signal; a memory cell array including a plurality of memory cells; and a control logic configured to control operations with respect to the plurality of memory cells, based on the command and the address buffered in the command/address buffer.

    Non-volatile memory device, controller and memory system
    9.
    发明授权
    Non-volatile memory device, controller and memory system 有权

    公开(公告)号：US11200932B2

    公开(公告)日：2021-12-14

    申请号：US16916345

    申请日：2020-06-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kuiyon Mun ,  Beomkyu Shin ,  Jaeyong Jeong

    IPC: G11C8/18 ,  G11C8/06 ,  G11C7/22 ,  G11C7/10

    Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a clock pin, a clock signal being received from a controller through the clock pin; a first input/output pin; a second input/output pin, data being received from the controller in synchronization with the clock signal through the second input/output pin; a command/address buffer configured to operate at a first operating speed and buffer a command and an address received through the first input/output pin in synchronization with the clock signal; a memory cell array including a plurality of memory cells; and a control logic configured to control operations with respect to the plurality of memory cells, based on the command and the address buffered in the command/address buffer.

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