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    SEMICONDUCTOR DEVICE
    4.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240266257A1

    公开(公告)日：2024-08-08

    申请号：US18382545

    申请日：2023-10-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungmin LIM ,  Jinnam KIM ,  Jongmin BAEK ,  Hyoseok CHOI

    IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

    CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

    Abstract: A semiconductor device includes a substrate having a front surface including an active region and a rear surface opposite to the front surface. An active pattern is on the active region. A gate structure extends in a second direction on the active region. Source/drain regions are disposed on the active pattern on both sides of the gate structure. A front interconnection structure is disposed on the gate structure and the source/drain regions. A rear interconnection structure is disposed on the rear surface of the substrate. A target region defined by the source/drain regions and the active pattern includes a non-oxidizing material at a first concentration. The non-oxidizing material is injected during a high-pressure heat treatment process. A rear interconnection region defined by the substrate, the rear through-structure, and the rear interconnection structure includes the non-oxidizing material at a second concentration higher than the first concentration.

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220005763A1

    公开(公告)日：2022-01-06

    申请号：US17480615

    申请日：2021-09-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jangho LEE ,  Jongmin BAEK ,  Wookyung YOU ,  Kyu-Hee HAN ,  Suhyun BARK

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

    Abstract: Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure.

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230027640A1

    公开(公告)日：2023-01-26

    申请号：US17699496

    申请日：2022-03-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongmin BAEK ,  Junghoo SHIN ,  Sangshin JANG ,  Junghwan CHUN ,  Kyeongbeom PARK ,  Suhyun BARK

    IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

    Abstract: A semiconductor device includes a substrate having an active region, a first insulating layer on the substrate, a second insulating layer on the first insulating layer, an etch stop layer between the first insulating layer and the second insulating layer, a via contact in the first insulating layer and electrically connected to the active region, an interconnection electrode in the second insulating layer and electrically connected to the via contact, a conductive barrier layer on a side surface and a lower surface of the interconnection electrode and having an extension portion extending to a partial region of a side surface of the via contact, and a side insulating layer on a side region of the via contact below the extension portion of the conductive barrier layer, the side insulating layer including the same material as a material of the etch stop layer.

    MEMORY DEVICE WITH REDUCED READ DISTURBANCE AND METHOD OF OPERATING THE MEMORY DEVICE
    7.
    发明申请
    MEMORY DEVICE WITH REDUCED READ DISTURBANCE AND METHOD OF OPERATING THE MEMORY DEVICE 有权

    公开(公告)号：US20210027837A1

    公开(公告)日：2021-01-28

    申请号：US16803450

    申请日：2020-02-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongryul Kim ,  Taehui NA ,  Dueung KIM ,  Jongmin BAEK

    IPC: G11C11/56 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/4074

    Abstract: The memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row control circuit including a plurality of row switches corresponding to the word lines, a column control circuit including a plurality of column switches corresponding to the bit lines, and a control logic circuit configured to control pre-charge operations on a word line and a bit line of a selected memory cell and perform a control operation to float the word line and the bit line together after a pre-charge period during a data reading operation. One of the word line and the bit line is floated after the pre-charge period and the other one is pseudo-floated after the pre-charge period.

    SEMICONDUCTOR DEVICES
    9.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20230059177A1

    公开(公告)日：2023-02-23

    申请号：US17720571

    申请日：2022-04-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sangshin JANG ,  Wookyung YOU ,  Sangkoo KANG ,  Donghyun ROH ,  Koungmin RYU ,  Jongmin BAEK

    IPC: H01L23/528 ,  H01L23/532

    Abstract: A semiconductor device including a first conductive layer on a substrate, a second conductive layer on the first conductive layer, a contact structure between the first and second conductive layers, and a barrier structure surrounding a lower region of a side surface of the second conductive layer, wherein the contact structure includes a contact conductive layer having a first upper surface portion and a second upper surface extending from the first upper surface portion and being concave, and a gap-fill pattern fills a space between the second upper surface portion and the second conductive layer and includes a first gap-fill insulating layer including a metal element and a second gap-fill insulating layer including a silicon element, and the barrier structure includes a first etch stop layer and a barrier layer that include same materials as the first insulating material and the second insulating material, respectively, may be provided.

    RESISTIVE MEMORY DEVICES AND METHODS OF OPERATING RESISTIVE MEMORY DEVICES
    10.
    发明申请
    RESISTIVE MEMORY DEVICES AND METHODS OF OPERATING RESISTIVE MEMORY DEVICES 有权

    公开(公告)号：US20210020236A1

    公开(公告)日：2021-01-21

    申请号：US16745823

    申请日：2020-01-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongmin BAEK ,  Jinyoung KIM ,  Junho SHIN

    IPC: G11C13/00 ,  H01L27/24

    Abstract: A resistive memory includes a memory cell array, a write/read circuitry and a control circuitry. The memory cell array includes a plurality of resistive memory cells coupled to a plurality of word-lines and a plurality of bit-lines. The write/read circuitry is coupled to the memory cell array through a row decoder and a column decoder, the write/read circuitry performs a write operation to write write data in a target page of the memory cell array, and verifies the write operation by comparing read data read from the target page with the write data. The control circuitry controls at least one of the row decoder, the column decoder and the write/read circuitry to control a resistance which a selected memory cell experiences according to a distance from an access point to the selected memory cell in the memory cell array based on an address.

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