公开(公告)号：US20170076975A1

公开(公告)日：2017-03-16

申请号：US15359724

申请日：2016-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： WOOKYUNG YOU ,  JONGMIN BAEK ,  SANGHOON AHN ,  SANGHO RHA ,  NAEIN LEE

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02208 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02345 ,  H01L21/02348 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure describes semiconductor devices and methods of fabricating the same. The method includes forming an interlayer insulating layer on a substrate and forming conductive patterns in the interlayer insulating layer. A pore density of an upper portion of the interlayer insulating layer is higher than that of a lower portion of the interlayer insulating layer, and a pore density of an intermediate portion of the interlayer insulating layer gradually increases toward the upper portion of the interlayer insulating layer. An air gap is provided between the conductive patterns.

Abstract translation: 本公开描述了半导体器件及其制造方法。 该方法包括在衬底上形成层间绝缘层，并在层间绝缘层中形成导电图案。 层间绝缘层的上部的孔密度高于层间绝缘层的下部的孔密度，层间绝缘层的中间部分的孔密度朝向层间绝缘层的上部逐渐增加 。 在导电图案之间设置气隙。

公开(公告)号：US20220209103A1

公开(公告)日：2022-06-30

申请号：US17655589

申请日：2022-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGHOON AHN ,  Oik Kwon ,  Jeonghee Park ,  Kihyun Hwang

IPC: H01L43/08 ,  H01L27/22 ,  H01L27/24 ,  H01L45/00 ,  H01L43/12 ,  H01L43/10

Abstract: A variable resistance memory device is provided including a plurality of lower electrodes disposed on a substrate. A plurality of variable resistors are disposed on the plurality of lower electrodes. A plurality of upper electrodes are disposed on the plurality of variable resistors. An interlayer insulating layer fills a space in the plurality of variable resistors. An anti-oxidation layer is disposed between the plurality of variable resistors and the interlayer insulating layer. The anti-oxidation layer covers side surfaces of the plurality of variable resistors, and the anti-oxidation layer comprises silicon and/or carbon.

公开(公告)号：US20230170376A1

公开(公告)日：2023-06-01

申请号：US18046491

申请日：2022-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KIJOONG YOON ,  KEEWON KIM ,  MINKWAN KIM ,  SANGHOON AHN ,  HAJIN LIM ,  JONGMIN JEON ,  TAEKSOO JEON ,  JAESUNG HUR

IPC: H01L27/146

CPC classification number: H01L27/14685 ,  H01L27/14645 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463

Abstract: A method of fabricating an image sensor includes providing a substrate that includes a plurality of pixel regions, forming an anti-reflection layer on the substrate, forming color filters on the anti-reflection layer, where the color filters are spaced apart from each other by openings, forming pyrolytic polymer patterns between the color filters that fill the openings, forming a capping layer on the color filters and the pyrolytic polymer patterns, and performing a thermal treatment process that removes the pyrolytic polymer patterns and forms air gap regions between the color filters.

公开(公告)号：US20170323850A1

公开(公告)日：2017-11-09

申请号：US15659125

申请日：2017-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： SANGHO RHA ,  JONGMIN BAEK ,  WOOKYUNG YOU ,  SANGHOON AHN ,  NAEIN LEE

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/764

CPC classification number: H01L23/5226 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween.

公开(公告)号：US20160247759A1

公开(公告)日：2016-08-25

申请号：US15146112

申请日：2016-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGHO RHA ,  JONGMIN BAEK ,  WOOKYUNG YOU ,  SANGHOON AHN ,  NAEIN LEE

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween.

公开(公告)号：US20150332955A1

公开(公告)日：2015-11-19

申请号：US14606970

申请日：2015-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： WOOKYUNG YOU ,  JONGMIN BAEK ,  SANGHOON AHN ,  SANGHO RHA ,  NAEIN LEE

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02208 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02345 ,  H01L21/02348 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure describes semiconductor devices and methods of fabricating the same. The method includes forming an interlayer insulating layer on a substrate and forming conductive patterns in the interlayer insulating layer. A pore density of an upper portion of the interlayer insulating layer is higher than that of a lower portion of the interlayer insulating layer, and a pore density of an intermediate portion of the interlayer insulating layer gradually increases toward the upper portion of the interlayer insulating layer. An air gap is provided between the conductive patterns.

Abstract translation: 本公开描述了半导体器件及其制造方法。 该方法包括在衬底上形成层间绝缘层，并在层间绝缘层中形成导电图案。 层间绝缘层的上部的孔密度高于层间绝缘层的下部的孔密度，层间绝缘层的中间部分的孔密度朝向层间绝缘层的上部逐渐增加 。 在导电图案之间设置气隙。

公开(公告)号：US20220384340A1

公开(公告)日：2022-12-01

申请号：US17530206

申请日：2021-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNGHOO SHIN ,  JONGMIN BAEK ,  SANGHOON AHN ,  WOOJIN LEE ,  JUNHYUK LIM

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor integrated circuit device includes a substrate; a transistor on the substrate; an interlayer insulating film on the transistor; an insulating liner on the interlayer insulating film; a first insulating film on the insulating liner; and a first wiring layer on the interlayer insulating film and surrounded by the insulating liner. A height of a top surface of the first insulating film in a vertical direction from a main surface of the interlayer insulating film is different than a height of a top surface of the first wiring layer in the vertical direction. A step exists between the top surfaces of the first wiring layer and the first insulating film. A height of the first insulating film is greater than a height of the first wiring layer. A width of the first wiring layer gradually narrows as the first wiring layer extends upwards along the vertical direction.

公开(公告)号：US20170278797A1

公开(公告)日：2017-09-28

申请号：US15618811

申请日：2017-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： SANGHO RHA ,  JONGMIN BAEK ,  WOOKYUNG YOU ,  SANGHOON AHN ,  NAE-IN LEE

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/02 ,  H01L21/321 ,  H01L21/288 ,  H01L21/306 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/02178 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/288 ,  H01L21/306 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.

公开(公告)号：US20130175693A1

公开(公告)日：2013-07-11

申请号：US13723303

申请日：2012-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAE SOO KIM ,  JEEYONG KIM ,  VIET HA NGUYEN ,  JAIHYUK SONG ,  SANGHOON AHN ,  GILHEYUN CHOI

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, at least one transistor integrated with the substrate, an interlayer insulating layer on the substrate, a conductive line extending within the interlayer insulating layer and electrically connected to the transistor, and at least one capping layer containing carbon in an amount of about 2 to about 7.5 atomic percent. The capping layer may cover the interlayer insulating layer in which the conductive line extends.

Abstract translation: 半导体器件包括衬底，与衬底集成的至少一个晶体管，衬底上的层间绝缘层，在层间绝缘层内延伸并电连接到晶体管的导电线，以及至少一个含有碳的覆盖层 量为约2至约7.5原子％。 覆盖层可以覆盖导线延伸的层间绝缘层。