公开(公告)号：US12268022B2

公开(公告)日：2025-04-01

申请号：US17714695

申请日：2022-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum Kim ,  Dahye Kim ,  Dongmyoung Kim ,  Dongwoo Kim ,  Yongjun Nam ,  Sangmoon Lee ,  Ingyu Jang ,  Sujin Jung

IPC: H10D62/10 ,  H10D62/13 ,  H10D62/17

Abstract: A semiconductor device includes a substrate having an active region extending in a first direction; a gate structure disposed on the substrate, intersecting the active region, and extending in a second direction; channel layers disposed on the active region to be spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, and to be surrounded by the gate structure; source/drain regions disposed on both sides of the gate structure and connected to the channel layers; air gap regions located between the source/drain regions and the active region and spaced apart from each other in the third direction; and semiconductor layers alternately disposed with the air gap regions in the third direction and defining the air gap regions, wherein lower ends of the source/drain regions are located on a level lower than an uppermost air gap region.

公开(公告)号：US20240266256A1

公开(公告)日：2024-08-08

申请号：US18369527

申请日：2023-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmoon Lee ,  Jinbum Kim

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: The present disclosure provides semiconductor devices including a field effect transistor (FET) and methods of fabricating the same. In some embodiments, a semiconductor device includes a substrate, a lower power line buried in a lower portion of the substrate, a source/drain pattern on the substrate, and a backside contact that penetrates the substrate and electrically couples the lower power line to the source/drain pattern. The backside contact includes an epitaxial pattern coupled to a lower portion of the source/drain pattern, a contact plug coupled to the lower power line, and a metal-semiconductor compound layer between the epitaxial pattern and the contact plug. The epitaxial pattern includes a top surface that protrudes toward the source/drain pattern.

公开(公告)号：US20210151319A1

公开(公告)日：2021-05-20

申请号：US17006799

申请日：2020-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeom Kim ,  Dongwoo Kim ,  Jihye Yi ,  JinBum Kim ,  Sangmoon Lee ,  Seunghun Lee

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device is provided. The semiconductor device includes: an active region on a semiconductor substrate; a channel region on the active region; a source/drain region adjacent to the channel region on the active region; a gate structure overlapping the channel region, on the channel region; a contact structure on the source/drain region; a gate spacer between the contact structure and the gate structure; and a contact spacer surrounding a side surface of the contact structure. The source/drain region includes a first epitaxial region having a recessed surface and a second epitaxial region on the recessed surface of the first epitaxial region, and the second epitaxial region includes an extended portion, extended from a portion overlapping the contact structure in a vertical direction, in a horizontal direction and overlapping the contact spacer in the vertical direction.

公开(公告)号：US11006210B2

公开(公告)日：2021-05-11

申请号：US16202911

申请日：2018-11-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangchul Ko ,  Sangmoon Lee ,  Byeonggeun Cheon ,  Dongkyu Park ,  Donghyun Jung

IPC: H04R1/32 ,  H04R3/04 ,  H04R1/28 ,  H04S7/00

Abstract: An apparatus for outputting an audio signal includes: a channel processor configured to generate two or more channel signals from audio data; a signal processor configured to render the generated two or more channel signals; and a directional speaker configured to reproduced a rendered channel signal as an audible sound. The signal processor may include a frequency converter configured to generate a channel signal of a frequency domain by converting the generated two or more channel signals through frequency conversion, and a re-panner configured to change a channel gain of at least one of the generated channel signals by as much as an adjustment value for the channel gain, wherein the adjustment value is monotonically changed as a frequency of the channel signal of the frequency domain increases.

公开(公告)号：US12256564B2

公开(公告)日：2025-03-18

申请号：US18415765

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim ,  Dahye Kim ,  Seokhoon Kim ,  Jaemun Kim ,  Ilgyou Shin ,  Haejun Yu ,  Kyungin Choi ,  Kihyun Hwang ,  Sangmoon Lee ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H10D62/13 ,  H10D30/60 ,  H10D30/67 ,  H10D30/69 ,  H10D62/822 ,  H10D64/01 ,  H10D64/23 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85 ,  H10D84/90

Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

公开(公告)号：US20240321991A1

公开(公告)日：2024-09-26

申请号：US18503019

申请日：2023-11-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ingeon Hwang ,  Jinbum Kim ,  Hyojin Kim ,  Sangmoon Lee ,  Yongjun Nam ,  Taehyung Lee

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device includes a fin-type active region on a substrate, a nanosheet on a fin top surface of the fin-type active region, the nanosheet being apart from the fin top surface of the fin-type active region in a vertical direction, a gate line surrounding the nanosheet on the fin-type active region, and a source/drain region on the fin-type active region, the source/drain region being in contact with the nanosheet, wherein the nanosheet includes a multilayered sheet comprising a first outer semiconductor sheet, a core semiconductor sheet, and a second outer semiconductor sheet, which are sequentially stacked in the vertical direction.

公开(公告)号：US20230361215A1

公开(公告)日：2023-11-09

申请号：US18133730

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeom Kim ,  Daehong Ko ,  Jinbum Kim ,  Sangmoon Lee ,  Daeseop Byeon ,  Seran Park ,  Hyunsu Shin ,  Kiseok Lee ,  Chunghee Jo

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L29/66545 ,  H01L29/6656

Abstract: A semiconductor device including a substrate extending in a first direction and a second direction perpendicular to the first direction, a first active pattern protruding from a top surface of the substrate and extending in the first direction, an isolation pattern covering a sidewall of the first active pattern on the substrate, first silicon patterns spaced apart from each other in a third direction on the first active pattern, the third direction perpendicular to the first direction and second direction, a first source/drain layer extending in the third direction from a top surface of the first active pattern on the first active pattern, and in contact with sidewalls of the first silicon patterns, wherein a sidewall of the first source/drain layer in the second direction has a constant inclination with respect to the top surface of the substrate, and a gate structure extending in the second direction while filling a gap between the first silicon patterns on the substrate.

公开(公告)号：US11791400B2

公开(公告)日：2023-10-17

申请号：US17643935

申请日：2021-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun Kim ,  Gyeom Kim ,  Seung Hun Lee ,  Dahye Kim ,  Ilgyou Shin ,  Sangmoon Lee ,  Kyungin Choi

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L29/6656 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method includes forming an active pattern on a substrate, the active pattern comprising first semiconductor patterns and second semiconductor patterns, which are alternately stacked, forming a capping pattern on a top surface and a sidewall of the active pattern, performing a deposition process on the capping pattern to form an insulating layer, and forming a sacrificial gate pattern intersecting the active pattern on the insulating layer. The capping pattern has a crystalline structure and is in physical contact with sidewalls of the first semiconductor patterns and sidewalls of the second semiconductor patterns.

公开(公告)号：US11417731B2

公开(公告)日：2022-08-16

申请号：US17128153

申请日：2020-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim ,  Dahye Kim ,  Seokhoon Kim ,  Jaemun Kim ,  Ilgyou Shin ,  Haejun Yu ,  Kyungin Choi ,  Kihyun Hwang ,  Sangmoon Lee ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/161 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

公开(公告)号：US11177346B2

公开(公告)日：2021-11-16

申请号：US16666958

申请日：2019-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan Kim ,  Sunguk Jang ,  Pankwi Park ,  Sangmoon Lee ,  Sujin Jung

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device including an active fin that protrudes from a substrate and forms a plurality of recess regions spaced apart from each other, a gate pattern between the plurality of recess regions that covers a lateral surface and a top surface of the active fin, a plurality of source/drain patterns in the plurality of recess regions, and a diffusion reduction region adjacent to each of a plurality of bottoms of the plurality of recess regions and each of a plurality of sidewalls of the plurality of recess regions, the diffusion reduction region including a dopant having a lower diffusion coefficient than phosphorus (P).