公开(公告)号：US12256564B2

公开(公告)日：2025-03-18

申请号：US18415765

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim ,  Dahye Kim ,  Seokhoon Kim ,  Jaemun Kim ,  Ilgyou Shin ,  Haejun Yu ,  Kyungin Choi ,  Kihyun Hwang ,  Sangmoon Lee ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H10D62/13 ,  H10D30/60 ,  H10D30/67 ,  H10D30/69 ,  H10D62/822 ,  H10D64/01 ,  H10D64/23 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85 ,  H10D84/90

Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

公开(公告)号：US20230411458A1

公开(公告)日：2023-12-21

申请号：US18239660

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ilgyou Shin ,  Minyi Kim ,  Myung Gil Kang ,  Jinbum Kim ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H01L29/15 ,  H01L29/78 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/158 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/785

Abstract: A semiconductor device includes; a substrate including a first region and a second region, a first active pattern extending upward from the first region, a first superlattice pattern on the first active pattern, a first active fin centrally disposed on the first active pattern, a first gate electrode disposed on the first active fin, and first source/drain patterns disposed on opposing sides of the first active fin and on the first active pattern. The first superlattice pattern includes at least one first semiconductor layer and at least one first blocker-containing layer, and the first blocker-containing layer includes at least one of oxygen, carbon, fluorine and nitrogen.

公开(公告)号：US11791400B2

公开(公告)日：2023-10-17

申请号：US17643935

申请日：2021-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun Kim ,  Gyeom Kim ,  Seung Hun Lee ,  Dahye Kim ,  Ilgyou Shin ,  Sangmoon Lee ,  Kyungin Choi

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L29/6656 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method includes forming an active pattern on a substrate, the active pattern comprising first semiconductor patterns and second semiconductor patterns, which are alternately stacked, forming a capping pattern on a top surface and a sidewall of the active pattern, performing a deposition process on the capping pattern to form an insulating layer, and forming a sacrificial gate pattern intersecting the active pattern on the insulating layer. The capping pattern has a crystalline structure and is in physical contact with sidewalls of the first semiconductor patterns and sidewalls of the second semiconductor patterns.

公开(公告)号：US20230223438A1

公开(公告)日：2023-07-13

申请号：US18182893

申请日：2023-03-13

Applicant: Samsung Electronics Co, Ltd.

Inventor： Haejun YU ,  Kyungin Choi ,  Seung Hun Lee

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L27/092

CPC classification number: H01L29/0653 ,  H01L29/4991 ,  H01L29/42392 ,  H01L29/66553 ,  H01L27/092

Abstract: A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, the channel pattern including semiconductor patterns stacked and spaced apart from each other, a gate electrode extending across the channel pattern, and inner spacers between the gate electrode and the source/drain pattern. The semiconductor patterns include stacked first and second semiconductor patterns. The gate electrode includes first and second portions, which are sequentially stacked between the substrate and the first and second semiconductor patterns, respectively. The inner spacers include first and second air gaps, between the first and second portions of the gate electrode and the source/drain pattern. The largest width of the first air gap is larger than that of the second air gap.

公开(公告)号：US11616144B2

公开(公告)日：2023-03-28

申请号：US16412796

申请日：2019-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunguk Jang ,  Sujin Jung ,  Jinyeong Joe ,  Jeongho Yoo ,  Seung Hun Lee ,  Jongryeol Yoo

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/417 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: A semiconductor device includes a first active fin protruding from a substrate, a first gate pattern covering a side surface and a top surface of the first active fin, and first source/drain patterns at opposite sides of the first gate pattern, each of the first source/drain patterns including a first lower side and a second lower side spaced apart from each other, a first upper side extended from the first lower side, a second upper side extended from the second lower side. The first lower side may be inclined at a first angle relative to a top surface of the substrate, the second upper side may be inclined at a second angle relative to the top surface of the substrate, and the first angle may be greater than the second angle.

公开(公告)号：US11508751B2

公开(公告)日：2022-11-22

申请号：US17144458

申请日：2021-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namkyu Edward Cho ,  Seok Hoon Kim ,  Myung Il Kang ,  Geo Myung Shin ,  Seung Hun Lee ,  Jeong Yun Lee ,  Min Hee Choi ,  Jeong Min Choi

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/11582 ,  H01L21/768

Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.

公开(公告)号：US11417731B2

公开(公告)日：2022-08-16

申请号：US17128153

申请日：2020-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim ,  Dahye Kim ,  Seokhoon Kim ,  Jaemun Kim ,  Ilgyou Shin ,  Haejun Yu ,  Kyungin Choi ,  Kihyun Hwang ,  Sangmoon Lee ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/161 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

公开(公告)号：US10784379B2

公开(公告)日：2020-09-22

申请号：US15995414

申请日：2018-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok Hoon Kim ,  Dong Myoung Kim ,  Dong Suk Shin ,  Seung Hun Lee ,  Cho Eun Lee ,  Hyun Jung Lee ,  Sung Uk Jang ,  Edward Nam Kyu Cho ,  Min-Hee Choi

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/02 ,  H01L29/423 ,  H01L29/165 ,  H01L27/088 ,  H01L29/08 ,  H01L29/49 ,  H01L27/12

Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.

公开(公告)号：US20180114727A1

公开(公告)日：2018-04-26

申请号：US15818657

申请日：2017-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong ,  Seung Hun Lee ,  Pan Kwi Park ,  Seung Ryul Lee

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L21/823807 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/04 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696

Abstract: A CMOS circuit includes a partial GAA nFET and a partial GAA pFET. The nFET and the pFET each include a fin including a stack of nanowire-like channel regions and a dielectric separation region extending completely between first and second nanowire-like channel regions of the stack. The nFET and the pFET each also include a source electrode and a drain electrode on opposite sides of the fin, and a gate stack extending along a pair of sidewalls of the stack of nanowire-like channel regions. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer does not extend between the first and second nanowire-like channel regions. The channel heights of the nanowire-like channel regions of the partial GAA nFET and the partial GAA pFET are different.

公开(公告)号：US20180087198A1

公开(公告)日：2018-03-29

申请号：US15563550

申请日：2016-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Oh Kim ,  Seung Hun Lee ,  Jun Hyun Park ,  Sung Mo Lee ,  So Dam Han

IPC: D06F33/02 ,  D06F39/14 ,  D06F39/08 ,  D06F39/02 ,  D06F39/04 ,  D06F39/00 ,  D06F23/04 ,  D06F17/10 ,  D06F37/24 ,  D06F37/30 ,  D06F37/40 ,  D06F37/38

CPC classification number: D06F33/02 ,  D06F1/04 ,  D06F17/10 ,  D06F23/04 ,  D06F29/00 ,  D06F35/006 ,  D06F37/24 ,  D06F37/304 ,  D06F37/38 ,  D06F37/40 ,  D06F39/00 ,  D06F39/003 ,  D06F39/005 ,  D06F39/02 ,  D06F39/045 ,  D06F39/087 ,  D06F39/088 ,  D06F39/12 ,  D06F39/14 ,  D06F2202/085 ,  D06F2202/10 ,  D06F2202/12 ,  D06F2204/065 ,  D06F2204/084 ,  D06F2204/086 ,  D06F2204/10 ,  D06F2210/00 ,  D06F2212/02 ,  D06F2216/00 ,  D06F2220/00 ,  D06F2222/00

Abstract: Provided is a washing apparatus and a method of controlling the same. The washing apparatus includes a washing tub; and a controller configured to determine whether laundry put into the washing tub is wet laundry or dry laundry, and to determine a weight of the laundry in the washing tub through a detection of wet laundry weight or a detection of dry laundry weight, based on a result of the determination. The washing apparatus includes a washing tub; and a controller configured to detect a water level of washing water in the washing tub, configured to perform at least one of detecting a weight of wet laundry weight and dry laundry according to the water level, and configured to allow washing to be performed according to at least one result of the detection of the wet laundry weight and the dry laundry weight.