公开(公告)号：US09721930B2

公开(公告)日：2017-08-01

申请号：US15168236

申请日：2016-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyoungjoo Lee ,  Minsoo Kim ,  Teak Hoon Lee ,  Young Kun Jee

IPC: H01L23/52 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/49838 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A semiconductor package includes a first semiconductor chip stacked on a package substrate in which a first surface of the first semiconductor chip faces the package substrate and a second surface that is opposite to the first surface, a second semiconductor chip stacked on the first semiconductor chip that includes a third surface facing the first semiconductor chip and a fourth surface that is opposite to the third surface, and an integral adhesive structure that substantially continuously fills a first space between the package substrate and the first semiconductor chip and a second space between the first and second semiconductor chips. The integral adhesive structure includes an extension protruding from outer sidewalls of the first and second semiconductor chips. The extension has one continuously convex sidewall between a level of the first surface and a level of the fourth surface.

公开(公告)号：US11923343B2

公开(公告)日：2024-03-05

申请号：US18059747

申请日：2022-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung Yoo ,  Jayeon Lee ,  Jae-eun Lee ,  Yeongkwon Ko ,  Jin-woo Park ,  Teak Hoon Lee

IPC: H01L25/065 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/3157 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.

公开(公告)号：US10930613B2

公开(公告)日：2021-02-23

申请号：US16438505

申请日：2019-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Sick Park ,  Un Byoung Kang ,  Tae Hong Min ,  Teak Hoon Lee ,  Ji Hwan Hwang

IPC: H01L23/31 ,  H01L23/00 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip having a first through substrate via (TSV), a second semiconductor chip stacked on the first semiconductor chip and a first adhesive layer disposed between the first semiconductor chip and the second semiconductor chip. The second semiconductor chip includes a second through substrate via connected to the first through substrate via. A side surface of the first adhesive layer is recessed from side surfaces of the first and second semiconductor chips.

公开(公告)号：US12074141B2

公开(公告)日：2024-08-27

申请号：US17531115

申请日：2021-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hun Shin ,  Un Byoung Kang ,  Yeong Kwon Ko ,  Jong Ho Lee ,  Teak Hoon Lee ,  Jun Yeong Heo

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/49838 ,  H01L2225/06513 ,  H01L2225/06517

Abstract: There is provided a semiconductor device comprising a first semiconductor chip which includes a first chip substrate, and a first through via penetrating the first chip substrate, a second semiconductor chip disposed on the first semiconductor chip, and includes a second chip substrate, and a second through via penetrating the second chip substrate, and a connecting terminal disposed between the first semiconductor chip and the second semiconductor chip to electrically connect the first through via and the second through via. The semiconductor device further comprising an inter-chip molding material which includes a filling portion that fills between the first semiconductor chip and the second semiconductor chip and encloses the connecting terminal, an extension portion that extends along at least a part of a side surface of the second semiconductor chip, and a protruding portion protruding from the extension portion.

公开(公告)号：US11848293B2

公开(公告)日：2023-12-19

申请号：US17376616

申请日：2021-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunkyoung Seo ,  Teak Hoon Lee ,  Chajea Jo

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05008 ,  H01L2224/05084 ,  H01L2224/05111 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/16013 ,  H01L2224/81203 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/18161

Abstract: A semiconductor package includes a sequential stack of first and second semiconductor chips, and a first internal connection member that connects the first and second semiconductor chips to each other. The first semiconductor chip includes a first substrate that has a first top surface and a first bottom surface that are opposite to each other, and a first conductive pad on the first top surface. The second semiconductor chip includes a second substrate that has a second top surface and a second bottom surface that are opposite to each other, and a second conductive bump on the second bottom surface. The first internal connection member connects the first conductive pad to the second conductive bump. The first conductive pad has a first width in one direction. The second conductive bump has a second width in the one direction. The first width is smaller than the second width.

公开(公告)号：US12165991B2

公开(公告)日：2024-12-10

申请号：US18162878

申请日：2023-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon Ko ,  Un-Byoung Kang ,  Jaekyung Yoo ,  Teak Hoon Lee

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.

公开(公告)号：US12113050B2

公开(公告)日：2024-10-08

申请号：US17552614

申请日：2021-12-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Sick Park ,  Un-Byoung Kang ,  Jongho Lee ,  Teak Hoon Lee

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/06051 ,  H01L2224/061 ,  H01L2224/06519 ,  H01L2224/16147 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/3841

Abstract: Disclosed is a semiconductor package with increased thermal radiation efficiency, which includes: a first die having signal and dummy regions and including first vias in the signal region, a second die on the first die and including second vias in the signal region, first die pads on a top surface of the first die and coupled to the first vias, first connection terminals on the first die pads which couple the second vias to the first vias, second die pads in the dummy region and on the top surface of the first die, and second connection terminals on the second die pads and electrically insulated from the first vias and the second vias. Each of the second die pads has a rectangular planar shape whose major axis is provided along a direction that leads away from the signal region.

公开(公告)号：US11594499B2

公开(公告)日：2023-02-28

申请号：US17203007

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon Ko ,  Un-Byoung Kang ,  Jaekyung Yoo ,  Teak Hoon Lee

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/13

Abstract: A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.

公开(公告)号：US11538792B2

公开(公告)日：2022-12-27

申请号：US17140241

申请日：2021-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung Yoo ,  Jayeon Lee ,  Jae-eun Lee ,  Yeongkwon Ko ,  Jin-woo Park ,  Teak Hoon Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/13 ,  H01L23/498 ,  H01L25/00

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.