公开(公告)号：US20240120251A1

公开(公告)日：2024-04-11

申请号：US18213851

申请日：2023-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIN-WOO PARK ,  UN-BYOUNG KANG ,  CHUNGSUN LEE

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/3157 ,  H01L21/56 ,  H01L24/08 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/92125 ,  H10B80/00

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a base semiconductor chip, a chip structure on the base semiconductor chip, a connection terminal between the base semiconductor chip and the chip structure, and a molding layer surrounding the chip structure and the connection terminal. The chip structure includes a first semiconductor chip including a first frontside pad and a first backside pad, and a second semiconductor including a second frontside pad and a second backside pad. A lateral surface of the first semiconductor chip is aligned with that of the second semiconductor chip. The first backside pad and the second frontside pad partially overlap each other when viewed in plan while being in direct contact with each other. The first backside pad and the second frontside pad include the same metal and are formed into a single unitary piece.

公开(公告)号：US20230275052A1

公开(公告)日：2023-08-31

申请号：US18313560

申请日：2023-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： JU-IL CHOI ,  UN-BYOUNG KANG ,  JIN HO AN ,  JONGHO LEE ,  JEONGGI JIN ,  ATSUSHI FUJISAKI

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/03 ,  H01L2224/13113 ,  H01L2224/03614 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05016 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05144 ,  H01L2224/11849 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13155 ,  H01L2224/13144 ,  H01L2224/13139 ,  H01L2224/13147

Abstract: Semiconductor devices are provided. A semiconductor device includes an insulating layer and a conductive element in the insulating layer. The semiconductor device includes a first barrier pattern in contact with a surface of the conductive element and a surface of the insulating layer. The semiconductor device includes a second barrier pattern on the first barrier pattern. Moreover, the semiconductor device includes a metal pattern on the second barrier pattern. Related semiconductor packages are also provided.

公开(公告)号：US20250029955A1

公开(公告)日：2025-01-23

申请号：US18616418

申请日：2024-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihoon JUNG ,  UN-BYOUNG KANG ,  YEONGKWON KO ,  KUYOUNG KIM

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/48 ,  H10B80/00

Abstract: A semiconductor package includes: a buffer die; a plurality of memory dies stacked on the buffer die; a mold layer covering a portion of a top surface of the buffer die and lateral surfaces of the plurality of memory dies; and an inorganic layer disposed on the mold layer, wherein the inorganic layer covers at least a portion of the lateral surface of an uppermost memory die of the plurality of memory dies, wherein a top surface of the inorganic layer is substantially coplanar with a top surface of the uppermost memory die of the plurality of memory dies, and wherein the inorganic layer includes oxide or nitride.

公开(公告)号：US20240162193A1

公开(公告)日：2024-05-16

申请号：US18213852

申请日：2023-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongyo KIM ,  UN-BYOUNG KANG ,  SANG-SICK PARK ,  Hanmin LEE ,  Seungyoon JUNG

IPC: H01L25/065 ,  B23K26/38 ,  B23K26/40 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L25/0657 ,  B23K26/38 ,  B23K26/40 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  B23K2101/40 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06541

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first semiconductor chip, a lower adhesion layer on the first semiconductor chip, a second semiconductor chip on the lower adhesion layer, an upper adhesion layer on the second semiconductor chip, and a third semiconductor chip on the upper adhesion layer. The lower adhesion layer includes a first cutting surface connected to a top surface of the lower adhesion layer. The upper adhesion layer is in contact with the first cutting surface of the lower adhesion layer.

公开(公告)号：US20230230946A1

公开(公告)日：2023-07-20

申请号：US17939127

申请日：2022-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongyo KIM ,  UN-BYOUNG KANG ,  MINSOO KIM ,  SANG-SICK PARK ,  Seungyoon JUNG

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/08 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/81203 ,  H01L24/81 ,  H01L2924/3511 ,  H01L2924/182 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/1703 ,  H01L2224/17055 ,  H01L2224/17104 ,  H01L2224/17179 ,  H01L2224/17132 ,  H01L2224/16012 ,  H01L2224/16055 ,  H01L2224/16059 ,  H01L2224/16104 ,  H01L2224/0801 ,  H01L2224/08056 ,  H01L2224/08055 ,  H01L2224/0903 ,  H01L2224/09179 ,  H01L2224/09132 ,  H01L2224/73204

Abstract: A semiconductor package comprises a first die having a central region and a peripheral region that surrounds the central region; a plurality of through electrodes that penetrate the first die; a plurality of first pads at a top surface of the first die and coupled to the through electrodes; a second die on the first die; a plurality of second pads at a bottom surface of the second die, the bottom surface of the second die facing the top surface of the first die; a plurality of connection terminals that connect the first pads to the second pads; and a dielectric layer that fills a space between the first die and the second die and surrounds the connection terminals. A first width of each of the first pads in the central region may be greater than a second width of each of the first pads in the peripheral region. Each of the connection terminals may include a convex portion at a lateral surface thereof, which protrudes beyond a lateral surface of a respective first pad and a lateral surface of a respective second pad. The convex portion may protrude in a direction away from a center of the first die. Protruding distances of the convex portions may increase in a direction from the center of the first die toward an outside of the first die.

公开(公告)号：US20210125955A1

公开(公告)日：2021-04-29

申请号：US16992895

申请日：2020-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIHWAN SUH ,  UN-BYOUNG KANG ,  TAEHUN KIM ,  HYUEKJAE LEE ,  JIHWAN HWANG ,  SANG CHEON PARK

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.

公开(公告)号：US20250087612A1

公开(公告)日：2025-03-13

申请号：US18626272

申请日：2024-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNHYUN AN ,  UN-BYOUNG KANG ,  HYOJIN YUN ,  SEUNG HUN CHAE ,  JU-IL CHOI

IPC: H01L23/00

Abstract: The present disclosure relates to a conductive structure including: a conductive pad that includes a first seed layer having a first area and a second area surrounding the first area, and a first metal layer disposed on the first area of the first seed layer; and a conductive pillar disposed on the conductive pad, wherein a thickness of the conductive pad in an area vertically overlapping the first area of the first seed layer is thicker than a thickness of the conductive pad in an area vertically overlapping the second area of the first seed layer, a semiconductor chip including the conductive structure, and a manufacturing method of the conductive structure.

公开(公告)号：US20250029941A1

公开(公告)日：2025-01-23

申请号：US18439381

申请日：2024-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNSU HWANG ,  UN-BYOUNG KANG ,  KUYOUNG KIM ,  JUMYONG PARK ,  DONGJOON OH ,  SANGHOO CHO

IPC: H01L23/00

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a substrate, a seed layer on the substrate, and a wiring pad on the seed layer. The wiring pad includes a pad portion, and a capping layer on the seed layer and covering a top surface and a lateral surface of the pad portion. A bottom surface of the pad portion is in contact with a top surface of the seed layer. A width of the top surface of the pad portion is greater than a width of the bottom surface of the pad portion.

公开(公告)号：US20230111854A1

公开(公告)日：2023-04-13

申请号：US17851245

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JU-IL CHOI ,  UN-BYOUNG KANG ,  MINSEUNG YOON ,  YONGHOE CHO ,  JEONGGI JIN ,  YUN SEOK CHOI

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48

Abstract: Provided is a semiconductor package, including a first redistribution substrate, a first semiconductor chip on the first redistribution substrate, first bumps between the first redistribution substrate and the first semiconductor chip, a conductive structure on the first redistribution substrate and spaced apart from the first semiconductor chip, a second redistribution substrate on the first semiconductor chip, second bumps between the first semiconductor chip and the second redistribution substrate, a second semiconductor chip on the second redistribution substrate, a first mold layer between the first redistribution substrate and the second redistribution substrate, and on the first semiconductor chip, and a second mold layer on the second redistribution substrate and the second semiconductor chip, and spaced apart from the first mold layer.

公开(公告)号：US20220028834A1

公开(公告)日：2022-01-27

申请号：US17245913

申请日：2021-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUEKJAE LEE ,  UN-BYOUNG KANG ,  SANG CHEON PARK ,  JINKYEONG SEOL ,  SANGHOON LEE

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package is provided. The semiconductor package may include a first semiconductor die, a second semiconductor die stacked on the first semiconductor die, the second semiconductor die having a width smaller than a width of the first semiconductor die, a third semiconductor die stacked on the second semiconductor die, the third semiconductor die having a width smaller than the width of the first semiconductor die, and a mold layer covering side surfaces of the second and third semiconductor dies and a top surface of the first semiconductor die. The second semiconductor die may include a second through via, and the third semiconductor die may include a third conductive pad in contact with the second through via.