公开(公告)号：US20240194752A1

公开(公告)日：2024-06-13

申请号：US18502352

申请日：2023-11-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Kyung YOU ,  Sang Koo KANG ,  Jun Chae LEE ,  Koung Min RYU ,  Woo Jin LEE

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate, an active pattern disposed on the substrate and extending in a first direction, gate electrodes covering the active pattern and extending in a second direction, a gate spacer disposed on a sidewall of each of the gate electrodes, a source/drain pattern disposed between adjacent ones of the gate electrodes, an etch stop film disposed along a sidewall of the gate spacer and a profile of the source/drain pattern, an interlayer insulating film disposed between the adjacent ones of the gate electrodes with a contact trench exposing the source/drain pattern defined therein, a liner film disposed on an outer sidewall of the contact trench, and a source/drain contact disposed on the liner film and filling the contact trench, in which the source/drain contact is connected to the source/drain pattern. At least a portion of the liner film may be disposed in the source/drain pattern.

公开(公告)号：US20170213786A1

公开(公告)日：2017-07-27

申请号：US15333508

申请日：2016-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hoon AHN ,  Tae Soo KIM ,  Jong Min BAEK ,  Woo Kyung YOU ,  Thomas OSZINDA ,  Byung Hee KIM ,  Nae In LEE

IPC: H01L23/498 ,  H01L23/535

CPC classification number: H01L23/53295 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.

公开(公告)号：US20190043803A1

公开(公告)日：2019-02-07

申请号：US15840128

申请日：2017-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Kyung YOU ,  Eui Bok LEE ,  Jong Min BAEK ,  Su Hyun BARK ,  Jang Ho LEE ,  Sang Hoon AHN ,  Hyeok Sang OH

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising a lower wire, an etch stop layer on the substrate, an interlayer insulating layer on the etch stop layer, an upper wire disposed in the interlayer insulating layer and separated from the lower wire and a via formed in the interlayer insulating layer and the etch stop layer and connecting the lower wire with the upper wire, wherein the via comprises a first portion in the etch stop layer and a second portion in the interlayer insulating layer, and wherein a sidewall of the first portion of the via increases stepwise.

公开(公告)号：US20190019759A1

公开(公告)日：2019-01-17

申请号：US16135234

申请日：2018-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Hoon AHN ,  Tae Soo KIM ,  Jong Min BAEK ,  Woo Kyung YOU ,  Thomas OSZINDA ,  Byung Hee KIM ,  Nae In LEE

IPC: H01L23/532

Abstract: A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.

公开(公告)号：US20170162431A1

公开(公告)日：2017-06-08

申请号：US15353984

申请日：2016-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hoon AHN ,  Jong Min BAEK ,  Myung Geun SONG ,  Woo Kyung YOU ,  Byung Kwon CHO ,  Byung Hee KIM ,  Na Ein LEE

IPC: H01L21/768 ,  H01L21/3205 ,  H01L23/528 ,  H01L21/311

CPC classification number: H01L21/7682 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295

Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.

公开(公告)号：US20240204107A1

公开(公告)日：2024-06-20

申请号：US18532230

申请日：2023-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Koo KANG ,  Woo Kyung YOU ,  Min Jae KANG ,  Koung Min RYU ,  Hoon Seok SEO ,  Woo Jin LEE ,  Jun Chae LEE

IPC: H01L29/786 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/0886 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes: a substrate including an upper side and a lower side; first and second active patterns spaced apart from each other; a field insulating film covering side walls of the first and second active patterns; a power rail disposed adjacent to a first side wall of the second active pattern and between the first active pattern and the second active pattern; a power rail via disposed on the power rail and connected to the power rail; a semiconductor etching stop pattern disposed adjacent to a second side wall of the second active pattern; and a first semiconductor pattern disposed on the semiconductor etching stop pattern, wherein a lower surface of the semiconductor etching stop pattern is disposed on substantially a same plane as the lower side of the substrate, and wherein at least part of the first semiconductor pattern is disposed in the field insulating film.

公开(公告)号：US20240112949A1

公开(公告)日：2024-04-04

申请号：US18537896

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Jin KANG ,  Jong Min BAEK ,  Woo Kyung YOU ,  Kyu-Hee HAN ,  Han Seong KIM ,  Jang Ho LEE ,  Sang Shin JANG

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76808 ,  H01L23/481 ,  H01L21/76832

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

公开(公告)号：US20210020497A1

公开(公告)日：2021-01-21

申请号：US16798789

申请日：2020-02-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Jin KANG ,  Jong Min BAEK ,  Woo Kyung YOU ,  Kyu-Hee HAN ,  Han Seong KIM ,  Jang Ho LEE ,  Sang Shin JANG

IPC: H01L21/768 ,  H01L23/48

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

公开(公告)号：US20190181088A1

公开(公告)日：2019-06-13

申请号：US16039838

申请日：2018-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok Lee ,  Deok Young JUNG ,  Sang Bom KANG ,  Doo-Hwan PARK ,  Jong Min BAEK ,  Sang Hoon AHN ,  Hyeok Sang OH ,  Woo Kyung YOU

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer. The first insulating film and the second insulating film may be sequentially stacked on the substrate in a vertical direction, and a longest vertical distance between an upper surface of the lower metal layer and the substrate may be less than a longest vertical distance between the upper surface of the second insulating film and the substrate.

公开(公告)号：US20220285207A1

公开(公告)日：2022-09-08

申请号：US17826366

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Jin KANG ,  Jong Min BAEK ,  Woo Kyung YOU ,  Kyu-Hee HAN ,  Han Seong KIM ,  Jang Ho LEE ,  Sang Shin JANG

IPC: H01L21/768 ,  H01L23/48

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.