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    WIRING SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
    2.
    发明申请
    WIRING SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME 有权

    公开(公告)号：US20240421093A1

    公开(公告)日：2024-12-19

    申请号：US18419469

    申请日：2024-01-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： YOUNGBAE KIM

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H10B80/00

    Abstract: Embodiments of a wiring substrate is provided. Embodiments include a first redistribution layer, a first core layer disposed on the first redistribution layer, a second core layer disposed on the first core layer, a first adhesion layer disposed between the first core layer and the second core layer, and a second redistribution layer disposed on the second core layer. In some cases, the first core layer includes a first core section and a first core pad disposed on a top surface of the first core section, wherein the second core layer includes a second core section and a second core pad disposed on a bottom surface of the second core section. The first core layer and the second core layer are electrically connected to each other through the first core pad and the second core pad.

    SEMICONDUCTOR DEVICES
    3.
    发明申请
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20190325930A1

    公开(公告)日：2019-10-24

    申请号：US16460284

    申请日：2019-07-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SUNGWOO KIM ,  BONG-SOO KIM ,  YOUNGBAE KIM ,  KIJAE HUR ,  GWANHYEOB KOH ,  HYEONGSUN HONG ,  YOOSANG HWANG

    IPC: G11C11/00 ,  G11C5/02 ,  G11C14/00 ,  H01L27/108 ,  H01L23/528 ,  H01L27/24 ,  H01L49/02 ,  H01L45/00

    Abstract: A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed next to each other on a substrate; and a second memory section laterally spaced apart from the first memory section, the second peripheral circuit section and the second memory section disposed next to each other on the substrate, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, and the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, wherein the second memory cells are higher from the substrate than each of the capacitors.

    SEMICONDUCTOR PACKAGE
    4.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250029927A1

    公开(公告)日：2025-01-23

    申请号：US18419266

    申请日：2024-01-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YOUNGBAE KIM

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

    Abstract: A semiconductor package includes a package substrate, a first device on the package substrate and a second device on the package substrate and horizontally spaced apart from the first device, where the package substrate includes a first redistribution layer, a second redistribution layer on the first redistribution layer, a core section between the first redistribution layer and the second redistribution layer, a dummy structure in the first redistribution layer and on a bottom surface of the core section and a bridge chip in the second redistribution layer and on a top surface of the core section, and where a thermal conductance of the dummy structure is greater than a thermal conductance of the first redistribution layer.

    NONVOLATILE MEMORY DEVICE
    5.
    发明申请
    NONVOLATILE MEMORY DEVICE 审中-公开

    公开(公告)号：US20200381478A1

    公开(公告)日：2020-12-03

    申请号：US16780014

    申请日：2020-02-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： SI-HO SONG ,  YOUNGBAE KIM ,  DUEUNG KIM ,  CHANGHYUN CHO

    IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

    Abstract: A nonvolatile memory device includes a memory cell array, a word line drive block that is connected to a first group of memory cells through a first group of word lines and to a second group of memory cells through a second group of word lines, a bit line bias and sense block that is connected to the first and second groups of memory cells through bit lines, a variable current supply block that generates a word line current to be supplied to a selected word line, and a control logic block that receives an address and a command and controls the variable current supply block to adjust an amount of the word line current based on the address. The control logic block further varies the amount of the word line current depending on a distance between the selected word line and the substrate.

    SEMICONDUCTOR PACKAGE
    7.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20240421136A1

    公开(公告)日：2024-12-19

    申请号：US18410400

    申请日：2024-01-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YOUNGBAE KIM

    IPC: H01L25/10 ,  H01L23/498 ,  H01L23/538 ,  H10B80/00

    Abstract: A semiconductor package includes a package substrate. A first device is on the package substrate. A second device is on the package substrate and is horizontally spaced apart from the first device. The package substrate includes a core portion. A bridge chip is on a top surface of the core portion. The bridge chip has first pads. An upper buildup portion covers the top surface of the core portion and surrounds the bridge chip. The upper buildup portion has second pads. First solders couple the first device to the first pads and second solders couple the first device to the second pads. A first height of the first solders is less than a second height of the second solders. A first interval between adjacent first solders of the first solders is less than a second interval between adjacent second solders of the second solders.

    SEMICONDUCTOR PACKAGE
    8.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220415758A1

    公开(公告)日：2022-12-29

    申请号：US17658614

    申请日：2022-04-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YOUNGBAE KIM ,  SUNGWOO PARK

    IPC: H01L23/495 ,  H01L23/00

    Abstract: A semiconductor package includes: a lead frame that includes a first surface and a second surface opposite to the first surface, where the lead frame includes a first lead that extends in a first direction, and a plurality of second leads that are spaced apart from the first lead on both sides of the first lead; at least one semiconductor chip mounted on the first surface of the lead frame by a plurality of bumps; and an encapsulant that encapsulates the lead frame and the at least one semiconductor chip, wherein the first lead has a groove in the first surface that partitions the plurality of bumps in contact with the first lead.

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