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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09559102B2

    公开(公告)日：2017-01-31

    申请号：US14976105

    申请日：2015-12-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yoonhae Kim ,  Myungil Kang ,  Sooyeon Jeong

    IPC: H01L29/78 ,  H01L27/092 ,  H01L27/088

    CPC classification number: H01L27/0922 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/785

    Abstract: A semiconductor device includes first and second active regions. Each active region includes a plurality of fin protrusions and a recessed area disposed between the fin protrusions. A plurality of gate structures are disposed on each of the plurality of fin protrusions. A semiconductor layer is disposed in each recessed area. A distance between the gate structures of the first active region is the same as a distance between the gate structures of the second active region, and a height difference between a bottom surface of the semiconductor layer of the first recessed area and a top surface of each of the fin protrusions of the first active region is smaller than a height difference between a bottom surface of the semiconductor layer of the recessed area of the second active region and a top surface of each of the fin protrusions of the second active region.

    Abstract translation: 半导体器件包括第一和第二有源区。 每个有源区域包括多个翅片突出部和设置在翅片突出部之间的凹陷区域。 多个栅极结构设置在多个翅片突起中的每一个上。 半导体层设置在每个凹陷区域中。 第一有源区域的栅极结构之间的距离与第二有源区域的栅极结构之间的距离与第一凹入区域的半导体层的底表面和每个第一有源区域的顶表面之间的高度差相同 第一有源区的鳍突起的距离小于第二有源区的凹陷区域的半导体层的底表面和第二有源区的每个鳍突起的顶表面之间的高度差。

    Semiconductor device having test structure
    3.
    发明授权
    Semiconductor device having test structure 有权

    公开(公告)号：US09337112B2

    公开(公告)日：2016-05-10

    申请号：US14725603

    申请日：2015-05-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ping Hsun Su ,  Yoonhae Kim ,  Hwasung Rhee

    IPC: H01L21/8234 ,  H01L21/66

    CPC classification number: H01L22/34

    Abstract: A semiconductor device is provided. First and second pads are electrically connected to a plurality of test structures. Each test structure includes an active region, active patterns, gate electrodes and an electrode pattern. The active region includes a rounded corner portion. The active patterns protrudes from the semiconductor substrate and extends in parallel in a first direction. The gate electrodes crosses over the active patterns in a second direction. One gate electrode is electrically connected to the first pad. The electrode pattern is disposed at a side of the gate electrode electrically connected to the first pad. The electrode pattern is electrically connected to the second pad. The electrode pattern crosses over the active patterns. An overlapping area of the electrode pattern and the active patterns in each test structure is different from an overlapping area of the electrode pattern and the active patterns in other test structures.

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11133392B2

    公开(公告)日：2021-09-28

    申请号：US16243564

    申请日：2019-01-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyoseok Choi ,  Hwichan Jun ,  Yoonhae Kim ,  Chulsung Kim ,  Heungsik Park ,  Doo-Young Lee

    IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66

    Abstract: Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, a source/drain region in an upper portion of the active pattern at a side of the gate electrode, the source/drain region including a recess region at an upper region thereof, a contact electrically connected to the source/drain region, the contact including a lower portion provided in the recess region, and a metal silicide layer provided at a lower region of the recess region and between the source/drain region and the contact.

    Semiconductor device
    7.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US09691902B2

    公开(公告)日：2017-06-27

    申请号：US14990398

    申请日：2016-01-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myungil Kang ,  Yoonhae Kim ,  Byeongchan Lee

    IPC: H01L29/78 ,  H01L29/417 ,  H01L27/092 ,  H01L29/423

    CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/41725 ,  H01L29/4232 ,  H01L29/785

    Abstract: A semiconductor device includes a first pattern on a first active region, a second pattern on a second active region, and a third pattern on a third active region. The first pattern is spaced from the second pattern by a first interval corresponding to the width of a first recess between the first and second active regions. The second pattern is spaced from the third pattern by a second interval corresponding to the width of a second recess between the second and third active regions. The first, second, and third patterns includes gate patterns, and the first and second recesses include semiconductor material with a conductivity type different from the active regions. The semiconductor material in one recess extends higher than the semiconductor material in the other recess. The first, second, and third patterns have the same width, and the first and second recesses have different depths.

    Semiconductor device and method of forming the same
    9.
    发明授权
    Semiconductor device and method of forming the same 有权
    半导体器件及其形成方法

    公开(公告)号：US09349851B2

    公开(公告)日：2016-05-24

    申请号：US14140616

    申请日：2013-12-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yoonhae Kim ,  Hong Seong Kang ,  Junjie Xiong ,  Yoonseok Lee ,  Youshin Choi

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/51

    CPC classification number: H01L29/78 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66545

    Abstract: A semiconductor device includes a substrate having an active region and a device isolation layer defining the active region, a gate electrode on the active region, source/drain regions at the active region at both sides of the gate electrode, a buffer insulating layer on the device isolation layer, an etch stop layer formed on the buffer insulating layer and extending onto the gate electrode and the source/drain region, a first interlayer insulating layer on the etch stop layer, a first contact and a second contact penetrating the first interlayer insulating layer and the etch stop layer. The first contact and the second contact are spaced apart from each other and are in contact with the source/drain region and the buffer insulating layer, respectively.

    Abstract translation: 半导体器件包括具有有源区和限定有源区的器件隔离层的衬底，有源区上的栅电极，栅电极两侧的有源区的源/漏区， 器件隔离层，形成在缓冲绝缘层上并延伸到栅电极和源极/漏极区的蚀刻停止层，在蚀刻停止层上的第一层间绝缘层，第一接触和穿过第一层间绝缘的第二接触 层和蚀刻停止层。 第一触点和第二触点彼此间隔开并分别与源极/漏极区域和缓冲绝缘层接触。

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