公开(公告)号：US07160804B2

公开(公告)日：2007-01-09

申请号：US11174750

申请日：2005-07-05

申请人： Shian-Jyh Lin ,  Sheng-Tsung Chen ,  Neng-Tai Shih ,  Chien-Chang Huang ,  Chien-Jung Yang ,  Yi-Jung Chen

发明人： Shian-Jyh Lin ,  Sheng-Tsung Chen ,  Neng-Tai Shih ,  Chien-Chang Huang ,  Chien-Jung Yang ,  Yi-Jung Chen

IPC分类号： H01L21/4763

CPC分类号： H01L29/6659 ,  H01L21/324 ,  H01L29/7833

摘要： A method of fabricating a MOS transistor by millisecond annealing. A semiconductor substrate with a gate stack comprising a gate electrode overlying a gate dielectric layer on a top surface of a semiconductor substrate is provided. At least one implanting process is performed to form two doped regions on opposite sides of the gate electrode. Millisecond annealing activates dopants in the doped regions. The millisecond anneal includes rapid heating and rapid cooling within 1 to 50 milliseconds.

摘要翻译： 一种通过毫秒退火制造MOS晶体管的方法。 提供了具有栅叠层的半导体衬底，其包括覆盖半导体衬底的顶表面上的栅介质层的栅电极。 执行至少一个注入工艺以在栅电极的相对侧上形成两个掺杂区域。 毫秒退火激活掺杂区中的掺杂剂。 毫秒退火包括快速加热和1至50毫秒内的快速冷却。

公开(公告)号：US20060094178A1

公开(公告)日：2006-05-04

申请号：US11174750

申请日：2005-07-05

申请人： Shian-Jyh Lin ,  Sheng-Tsung Chen ,  Neng-Tai Shih ,  Chien-Chang Huang ,  Chien-Jung Yang ,  Yi-Jung Chen

发明人： Shian-Jyh Lin ,  Sheng-Tsung Chen ,  Neng-Tai Shih ,  Chien-Chang Huang ,  Chien-Jung Yang ,  Yi-Jung Chen

IPC分类号： H01L21/8234

CPC分类号： H01L29/6659 ,  H01L21/324 ,  H01L29/7833

摘要： A method of fabricating a MOS transistor by millisecond annealing. A semiconductor substrate with a gate stack comprising a gate electrode overlying a gate dielectric layer on a top surface of a semiconductor substrate is provided. At least one implanting process is performed to form two doped regions on opposite sides of the gate electrode. Millisecond annealing activates dopants in the doped regions. The millisecond anneal includes rapid heating and rapid cooling within 1 to 50 milliseconds.

摘要翻译： 一种通过毫秒退火制造MOS晶体管的方法。 提供了具有栅叠层的半导体衬底，其包括覆盖半导体衬底的顶表面上的栅介质层的栅电极。 执行至少一个注入工艺以在栅电极的相对侧上形成两个掺杂区域。 毫秒退火激活掺杂区中的掺杂剂。 毫秒退火包括快速加热和1至50毫秒内的快速冷却。

公开(公告)号：US20070131998A1

公开(公告)日：2007-06-14

申请号：US11679087

申请日：2007-02-26

申请人： Shian-Jyh Lin ,  Sheng-Tsung Chen ,  Neng-Tai Shih

发明人： Shian-Jyh Lin ,  Sheng-Tsung Chen ,  Neng-Tai Shih

IPC分类号： H01L29/94

CPC分类号： H01L27/10876 ,  H01L27/10841 ,  H01L27/10867

摘要： A vertical transistor device and fabrication method thereof are provided, the vertical transistor device comprising a substrate having a deep trench. A capacitor is disposed in a lower portion of the deep trench. A conductive structure is disposed on the capacitor inside the deep trench. An epitaxial layer, having an epitaxial sidewall region, is disposed on the substrate. A vertical gate structure is disposed on the conductive structure and adjacent to the epitaxial sidewall region of the epitaxial layer.

摘要翻译： 提供了一种垂直晶体管器件及其制造方法，该垂直晶体管器件包括具有深沟槽的衬底。 电容器设置在深沟槽的下部。 导电结构设置在深沟槽内的电容器上。 具有外延侧壁区域的外延层设置在基板上。 垂直栅极结构设置在导电结构上并与外延层的外延侧壁区相邻。

公开(公告)号：US20070096186A1

公开(公告)日：2007-05-03

申请号：US11366107

申请日：2006-03-01

申请人： Shian-Jyh Lin ,  Sheng-Tsung Chen ,  Neng-Tai Shih

发明人： Shian-Jyh Lin ,  Sheng-Tsung Chen ,  Neng-Tai Shih

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/10876 ,  H01L27/10841 ,  H01L27/10867

摘要： A vertical transistor device and fabrication method thereof are provided, the vertical transistor device comprising a substrate having a deep trench. A capacitor is disposed in a lower portion of the deep trench. A conductive structure is disposed on the capacitor inside the deep trench. An epitaxial layer, having an epitaxial sidewall region, is disposed on the substrate. A vertical gate structure is disposed on the conductive structure and adjacent to the epitaxial sidewall region of the epitaxial layer.

摘要翻译： 提供了一种垂直晶体管器件及其制造方法，该垂直晶体管器件包括具有深沟槽的衬底。 电容器设置在深沟槽的下部。 导电结构设置在深沟槽内的电容器上。 具有外延侧壁区域的外延层设置在基板上。 垂直栅极结构设置在导电结构上并与外延层的外延侧壁区相邻。

公开(公告)号：US07449382B2

公开(公告)日：2008-11-11

申请号：US11441313

申请日：2006-05-24

申请人： Meng-Hung Chen ,  Shian-Jyh Lin ,  Neng-Tai Shih

发明人： Meng-Hung Chen ,  Shian-Jyh Lin ,  Neng-Tai Shih

IPC分类号： H01L21/8242

CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/10841 ,  H01L27/10876 ,  H01L29/42392

摘要： A memory device is disclosed. A substrate is provided. A plurality of pillars is disposed on the substrate. Each pillar has a plurality of epitaxial layers, has a first sidewall and a second sidewall. A trench is formed between the pillars. A common bottom electrode is disposed in a lower portion of the trench and surrounded by a node dielectric layer. A first insulating layer is disposed on the common bottom electrode inside the trench. A plurality of gate structures is disposed on the first sidewall and inside the trench. A second insulating layer is disposed inside the trench and adjacent to the gate structures. A third insulating layer, body line, and fourth insulating layer are respectively disposed on the substrate and located between the second insulating layer and the second sidewall.

摘要翻译： 公开了一种存储器件。 提供基板。 多个支柱设置在基板上。 每个柱具有多个外延层，具有第一侧壁和第二侧壁。 在支柱之间形成沟槽。 公共底电极设置在沟槽的下部并被节点电介质层包围。 第一绝缘层设置在沟槽内的公共底部电极上。 多个栅极结构设置在第一侧壁和沟槽内。 第二绝缘层设置在沟槽内并与栅极结构相邻。 第三绝缘层，体线和第四绝缘层分别设置在基板上并且位于第二绝缘层和第二侧壁之间。

公开(公告)号：US20070166914A1

公开(公告)日：2007-07-19

申请号：US11441313

申请日：2006-05-24

申请人： Meng-Hung Chen ,  Shian-Jyh Lin ,  Neng-Tai Shih

发明人： Meng-Hung Chen ,  Shian-Jyh Lin ,  Neng-Tai Shih

IPC分类号： H01L21/8242

CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/10841 ,  H01L27/10876 ,  H01L29/42392

摘要： A memory device is disclosed. A substrate is provided. A plurality of pillars is disposed on the substrate. Each pillar has a plurality of epitaxial layers, has a first sidewall and a second sidewall. A trench is formed between the pillars. A common bottom electrode is disposed in a lower portion of the trench and surrounded by a node dielectric layer. A first insulating layer is disposed on the common bottom electrode inside the trench. A plurality of gate structures is disposed on the first sidewall and inside the trench. A second insulating layer is disposed inside the trench and adjacent to the gate structures. A third insulating layer, body line, and fourth insulating layer are respectively disposed on the substrate and located between the second insulating layer and the second sidewall.

摘要翻译： 公开了一种存储器件。 提供基板。 多个支柱设置在基板上。 每个柱具有多个外延层，具有第一侧壁和第二侧壁。 在支柱之间形成沟槽。 公共底电极设置在沟槽的下部并被节点电介质层包围。 第一绝缘层设置在沟槽内的公共底部电极上。 多个栅极结构设置在第一侧壁和沟槽内。 第二绝缘层设置在沟槽内并与栅极结构相邻。 第三绝缘层，体线和第四绝缘层分别设置在基板上并且位于第二绝缘层和第二侧壁之间。

公开(公告)号：US20100072449A1

公开(公告)日：2010-03-25

申请号：US12324841

申请日：2008-11-27

申请人： Chun-I Hsieh ,  Chang-Rong Wu ,  Neng-Tai Shih ,  Kou-Chen Liu

发明人： Chun-I Hsieh ,  Chang-Rong Wu ,  Neng-Tai Shih ,  Kou-Chen Liu

IPC分类号： H01L21/04 ,  H01L45/00

CPC分类号： H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16

摘要： A method for fabricating an RRAM is provided. First, a bottom electrode is formed. A resistive layer is formed on the bottom electrode. A top electrode is then formed on the resistive layer, wherein the top electrode is selected from the group consisting of indium tin oxide (ITO) and indium zinc oxide (IZO). Finally, the top electrode is irradiated with UV light.

摘要翻译： 提供了一种制造RRAM的方法。 首先，形成底部电极。 电阻层形成在底部电极上。 然后在电阻层上形成顶部电极，其中顶部电极选自氧化铟锡（ITO）和氧化铟锌（IZO）。 最后，用紫外光照射顶部电极。

公开(公告)号：US20050124111A1

公开(公告)日：2005-06-09

申请号：US10846321

申请日：2004-05-14

申请人： Cheng-Chih Huang ,  Sheng-Wei Yang ,  Neng-Tai Shih ,  Chen-Chou Huang

发明人： Cheng-Chih Huang ,  Sheng-Wei Yang ,  Neng-Tai Shih ,  Chen-Chou Huang

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/8238 ,  H01L21/20 ,  H01L21/8234 ,  H01L21/8244

CPC分类号： H01L28/40 ,  H01L27/10864 ,  H01L27/10867

摘要： A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided. A collar dielectric layer is conformally formed on the trench bottom portion, and the trench is filled with a conducting layer. The collar dielectric layer is etched below the level of the surface of the conducting layer to form a groove between the conducting layer and the trench. The groove is filled with a doped conducting layer. The dopant in the doped conducting layer is diffused to the semiconductor substrate in an ion diffusion area as a buried strap. The conducting layer and the doped conducting layer are etched below the ion diffusion area. A top trench insulating layer is formed on the bottom of the trench, wherein the top trench insulating layer is lower than the ion diffusion area.

公开(公告)号：US07408215B2

公开(公告)日：2008-08-05

申请号：US11696160

申请日：2007-04-03

申请人： Ming-Cheng Chang ,  Neng-Tai Shih

发明人： Ming-Cheng Chang ,  Neng-Tai Shih

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10841 ,  H01L27/0207 ,  H01L27/1087 ,  H01L27/10876

摘要： A DRAM structure on a silicon substrate has an active area, gate conductors, deep trench capacitors, and vertical transistors. The deep trench capacitors are formed at intersections of the active area and the gate conductors, and each deep trench capacitor is coupled electrically to the corresponding vertical transistor to form a memory cell. The transistor includes a gate, a source in a lateral side of the gate, and a drain in another lateral side of the gate The depth of the drain is different from the depth of the source.

摘要翻译： 硅衬底上的DRAM结构具有有源区，栅极导体，深沟槽电容器和垂直晶体管。 深沟槽电容器形成在有源区和栅极导体的交点处，并且每个深沟槽电容器电耦合到相应的垂直晶体管以形成存储单元。 晶体管包括栅极，栅极的侧面中的源极和栅极的另一侧面中的漏极漏极的深度不同于源极的深度。

公开(公告)号：US20050016948A1

公开(公告)日：2005-01-27

申请号：US10690999

申请日：2003-10-22

申请人： Sheng-Wei Yang ,  Neng-Tai Shih ,  Wen-Sheng Liao ,  Chih-How Chang

发明人： Sheng-Wei Yang ,  Neng-Tai Shih ,  Wen-Sheng Liao ,  Chih-How Chang

IPC分类号： H01L21/3105 ,  H01L21/311 ,  H01L21/316 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31612 ,  H01L21/76232

摘要： A method of fabricating a trench isolation with high aspect ratio. The method comprises the steps of: providing a substrate with a trench; depositing a first isolation layer filling the trench by low pressure chemical vapor deposition; etching the first isolation layer so that its surface is lowered to the opening of the trench; depositing a second isolation layer to fill the trench without voids by high density plasma chemical vapor deposition and achieving global planarization by chemical-mechanical polishing then providing a rapidly annealing procedure. Accordingly, the present invention achieves void-free trench isolation with high aspect ratio.