公开(公告)号：US20120199967A1

公开(公告)日：2012-08-09

申请号：US13209469

申请日：2011-08-15

Applicant: Simon Jonathan Stacey

Inventor： Simon Jonathan Stacey

IPC: H01L23/485 ,  H05K1/03

CPC classification number: H01L23/3114 ,  H01L23/3142 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/0519 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05647 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/13111 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electrical interconnect for connecting an IC chip to a PCB, the electrical interconnect comprising a plurality of connection elements for connection to the PCB attached to a first surface of the electrical interconnect, wherein the amount of thermal and/or mechanical stress that each solder element connection can take before failing is improved.

Abstract translation: 一种用于将IC芯片连接到PCB的电互连件，所述电互连件包括用于连接到所述电连接器的第一表面的PCB的多个连接元件，其中每个焊料元件的热和/或机械应力的量 连接可以在故障之前进行改进。

公开(公告)号：US20120001650A1

公开(公告)日：2012-01-05

申请号：US12974423

申请日：2010-12-21

Applicant: Simon Jonathan Stacey

Inventor： Simon Jonathan Stacey

IPC: G01R1/067 ,  B08B7/00

CPC classification number: B08B1/04 ,  G01R1/06722 ,  G01R1/06733 ,  G01R3/00

Abstract: A test probe is configured to provide conductive contact with a surface on application of the probe to the surface. The probe includes a probe body having a proximal and distal end, a probe tip located at the distal end of the probe body, the probe being configured such that, when the probe tip is applied to the surface, the probe tip is moved to rotate about its axis, whereby the shaft tip can rotatably remove oxidation and/or contamination debris from between the shaft tip and the surface.

Abstract translation: 测试探针被配置为在将探针应用于表面时提供与表面的导电接触。 探针包括具有近端和远端的探针主体，位于探针主体远端的探针尖端，探针构造成使得当探针尖端被施加到表面时，探针尖端被移动以旋转 围绕其轴线，由此轴尖端可旋转地从轴尖端和表面之间移除氧化和/或污染碎屑。

公开(公告)号：US08604568B2

公开(公告)日：2013-12-10

申请号：US13304968

申请日：2011-11-28

Applicant: Simon Jonathan Stacey

Inventor： Simon Jonathan Stacey

IPC: H01L29/84 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/24 ,  B81B2207/012 ,  B81B2207/095 ,  B81C1/0023 ,  B81C2203/0154 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/73217 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for forming a stacked integrated circuit package of primary dies on a carrier die, includes forming electrically conductive pillars at connection pads defined on an active face of a carrier wafer incorporating carrier integrated circuits, the electrically conductive pillars providing electrical connections to said carrier integrated circuits; attaching primary dies to the active face of the carrier wafer, each supporting electrically conductive pillars at connection pads defined on an active face of the primary die; encapsulating the active face of the carrier wafer and the primary dies attached thereto in an insulating material; producing a wafer package by removing a thickness of the insulating layer sufficient to expose the electrically conductive pillars; and singulating the carrier wafer to form stacked integrated circuit packages, each package comprising at least one primary die on a carrier die.

Abstract translation: 一种用于在载体裸片上形成初级管芯的层叠集成电路封装的方法，包括在包含载流子集成电路的载体晶片的有源面上限定的连接焊盘处形成导电柱，所述导电柱提供与所述载体集成的电连接 电路; 将初级管芯附接到载体晶片的有效面上，每个支撑在主模具的有效面上的连接焊盘处支撑导电柱; 将载体晶片的主动面和附着于其上的主模具封装在绝缘材料中; 通过去除足以暴露导电柱的绝缘层的厚度来制造晶片封装; 并且分离载体晶片以形成堆叠集成电路封装，每个封装在载体裸片上包括至少一个主要裸片。

公开(公告)号：US20120139068A1

公开(公告)日：2012-06-07

申请号：US13304968

申请日：2011-11-28

Applicant: Simon Jonathan Stacey

Inventor： Simon Jonathan Stacey

IPC: H01L29/84 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/24 ,  B81B2207/012 ,  B81B2207/095 ,  B81C1/0023 ,  B81C2203/0154 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/73217 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for forming a stacked integrated circuit package of primary dies on a carrier die, includes forming electrically conductive pillars at connection pads defined on an active face of a carrier wafer incorporating carrier integrated circuits, the electrically conductive pillars providing electrical connections to said carrier integrated circuits; attaching primary dies to the active face of the carrier wafer, each supporting electrically conductive pillars at connection pads defined on an active face of the primary die; encapsulating the active face of the carrier wafer and the primary dies attached thereto in an insulating material; producing a wafer package by removing a thickness of the insulating layer sufficient to expose the electrically conductive pillars; and singulating the carrier wafer to form stacked integrated circuit packages, each package comprising at least one primary die on a carrier die.

Abstract translation: 一种用于在载体裸片上形成初级管芯的层叠集成电路封装的方法，包括在包含载流子集成电路的载体晶片的有源面上限定的连接焊盘处形成导电柱，所述导电柱提供与所述载体集成的电连接 电路; 将初级管芯附接到载体晶片的有效面上，每个支撑在主模具的有效面上的连接焊盘处支撑导电柱; 将载体晶片的主动面和附着于其上的主模具封装在绝缘材料中; 通过去除足以暴露导电柱的绝缘层的厚度来制造晶片封装; 并且分离载体晶片以形成堆叠集成电路封装，每个封装在载体裸片上包括至少一个主要裸片。

公开(公告)号：US09177885B2

公开(公告)日：2015-11-03

申请号：US12518262

申请日：2007-11-26

Applicant: Simon Jonathan Stacey

Inventor： Simon Jonathan Stacey

IPC: H01L23/32 ,  H01L23/31 ,  H01L23/28 ,  H01L23/532 ,  H01L23/29 ,  H01L23/00

CPC classification number: H01L24/17 ,  H01L23/28 ,  H01L23/29 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/532 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13111 ,  H01L2224/1412 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A device comprising a chip including a substrate defining one or more electronic devices and a printed circuit board electrically connected to the chip via one or more solder elements sandwiched between the chip and the printed circuit board, and the solder elements, said buffer layers having a Young's Modulus of 2.5GPa or less.

Abstract translation: 一种包括芯片的器件，其包括限定一个或多个电子器件的衬底和经由夹在所述芯片和所述印刷电路板之间的一个或多个焊料元件与所述芯片电连接的印刷电路板，所述缓冲层具有 杨氏模量2.5GPa以下。

公开(公告)号：US20100013093A1

公开(公告)日：2010-01-21

申请号：US12518262

申请日：2007-11-26

Applicant: Simon Jonathan Stacey

Inventor： Simon Jonathan Stacey

IPC: H01L23/498

CPC classification number: H01L24/17 ,  H01L23/28 ,  H01L23/29 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/532 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13111 ,  H01L2224/1412 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A device comprising a chip including a substrate defining one or more electronic devices and a printed circuit board electrically connected to the chip via one or more solder elements sandwiched between the chip and the printed circuit board, and the solder elements, said buffer layers having a Young's Modulus of 2.5 GPa or less.

Abstract translation: 一种包括芯片的器件，其包括限定一个或多个电子器件的衬底和经由夹在所述芯片和所述印刷电路板之间的一个或多个焊料元件与所述芯片电连接的印刷电路板，所述缓冲层具有 年轻模量为2.5GPa以下。

公开(公告)号：US09087795B2

公开(公告)日：2015-07-21

申请号：US13209469

申请日：2011-08-15

Applicant: Simon Jonathan Stacey

Inventor： Simon Jonathan Stacey

IPC: H01L23/485 ,  H05K1/03 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/3114 ,  H01L23/3142 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/0519 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05647 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/13111 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electrical interconnect for connecting an IC chip to a PCB, the electrical interconnect comprising a plurality of connection elements for connection to the PCB attached to a first surface of the electrical interconnect, wherein the amount of thermal and/or mechanical stress that each solder element connection can take before failing is improved.

Abstract translation: 一种用于将IC芯片连接到PCB的电互连件，所述电互连件包括用于连接到所述电连接器的第一表面的PCB的多个连接元件，其中每个焊料元件的热和/或机械应力的量 连接可以在故障之前进行改进。

公开(公告)号：US08183143B2

公开(公告)日：2012-05-22

申请号：US12675253

申请日：2008-08-07

Applicant: Simon Jonathan Stacey

Inventor： Simon Jonathan Stacey

IPC: H01L21/44

CPC classification number: H01L24/11 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/11334 ,  H01L2224/11472 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H05K3/3478 ,  H05K2203/041 ,  H05K2203/0557 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of providing connections to a chip having contact pads on the surface thereof, comprising: locating a discrete solder element on each pad; and melting the discrete solder elements so as to cause each of them to adhere to the respective pad, thereby forming a solder bump extending from the surface of the chip; wherein the size of each discrete solder element relative to the area of the pad on which it is located is such that the height of each bump is less than 70% of the diameter of the solder element that formed it.

Abstract translation: 提供与具有其表面上的接触焊盘的芯片的连接的方法，包括：在每个焊盘上定位分立焊料元件; 并且使分散的焊锡元件熔化以使其各自粘附到相应的焊盘，从而形成从芯片的表面延伸的焊料凸块; 其中每个离散焊料元件相对于其所在的焊盘区域的尺寸使得每个凸块的高度小于形成焊料元件的直径的70％。

公开(公告)号：US20100210101A1

公开(公告)日：2010-08-19

申请号：US12675253

申请日：2008-08-07

Applicant: Simon Jonathan Stacey

Inventor： Simon Jonathan Stacey

IPC: H01L21/60

CPC classification number: H01L24/11 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/11334 ,  H01L2224/11472 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H05K3/3478 ,  H05K2203/041 ,  H05K2203/0557 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of providing connections to a chip having contact pads on the surface thereof, comprising: locating a discrete solder element on each pad; and melting the discrete solder elements so as to cause each of them to adhere to the respective pad, thereby forming a solder bump extending from the surface of the chip; wherein the size of each discrete solder element relative to the area of the pad on which it is located is such that the height of each bump is less than 70% of the diameter of the solder element that formed it.

Abstract translation: 提供与具有其表面上的接触焊盘的芯片的连接的方法，包括：在每个焊盘上定位分立焊料元件; 并且使分散的焊锡元件熔化以使其各自粘附到相应的焊盘，从而形成从芯片的表面延伸的焊料凸块; 其中每个离散焊料元件相对于其所在的焊盘区域的尺寸使得每个凸块的高度小于形成焊料元件的直径的70％。

公开(公告)号：US20100096730A1

公开(公告)日：2010-04-22

申请号：US12568233

申请日：2009-09-28

Applicant: Simon Jonathan Stacey

Inventor： Simon Jonathan Stacey

IPC: H01L21/304 ,  H01L23/58

CPC classification number: H01L21/78 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/564 ,  H01L23/585 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2924/0002 ,  H01L2224/05552

Abstract: A method of semiconductor wafer fabrication. The wafer is fabricated by receiving a semiconductor wafer having a substrate layer and at least one processed layer, cutting a trench into the wafer, wherein the trench penetrates through the at least one processed layer and only partially through the thickness of the substrate layer, and depositing a passivation layer over the at least one processed layer such that the trench is filled with the passivation material.

Abstract translation: 一种半导体晶片制造方法。 通过接收具有衬底层和至少一个处理层的半导体晶片来制造晶片，将沟槽切割到晶片中，其中沟槽穿过至少一个处理层并且仅部分地穿过衬底层的厚度，以及 在所述至少一个处理层上沉积钝化层，使得所述沟槽被所述钝化材料填充。