公开(公告)号：US11923239B2

公开(公告)日：2024-03-05

申请号：US17663898

申请日：2022-05-18

Applicant: Soitec

Inventor： Eric Desbonnets ,  Ionut Radu ,  Oleg Kononchuk ,  Jean-Pierre Raskin

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L21/76283 ,  H01L21/02002 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1218 ,  H01L29/0649 ,  H01L29/78603 ,  H01L21/76264

Abstract: Substrates for microelectronic radiofrequency devices may include a substrate comprising a semiconductor material. Trenches may be located in an upper surface of the substrate, at least some of the trenches including a filler material located within the respective trench. A resistivity of the filler material may be 10 kOhms·cm or greater. A piezoelectric material may be located on or above the upper surface of the substrate. Methods of making substrates for microelectronic radiofrequency devices may involve forming trenches in an upper surface of a substrate including a semiconductor material. A filler material may be placed in at least some of the trenches, and a piezoelectric material may be placed on or above the upper surface of the substrate.

公开(公告)号：US11595020B2

公开(公告)日：2023-02-28

申请号：US16877309

申请日：2020-05-18

Applicant: Soitec

Inventor： Arnaud Castex ,  Daniel Delprat ,  Bernard Aspar ,  Ionut Radu

IPC: H03H9/02 ,  H03H3/04 ,  H03H3/10 ,  H01L41/312 ,  H01L41/08 ,  H01L41/313 ,  H01L41/187 ,  H01L41/47 ,  H01L41/332 ,  H01L41/337 ,  H03H9/64

Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

公开(公告)号：US11205702B2

公开(公告)日：2021-12-21

申请号：US16086275

申请日：2017-03-31

Applicant: Soitec

Inventor： Christophe Figuet ,  Ludovic Ecarnot ,  Bich-Yen Nguyen ,  Walter Schwarzenbach ,  Daniel Delprat ,  Ionut Radu

IPC: H01L29/161 ,  H01L23/00 ,  H01L21/306

Abstract: A method for manufacturing a structure comprising a first substrate comprising at least one electronic component likely to be damaged by a temperature higher than 400° C. and a semiconductor layer extending on the first substrate comprises: (a) providing a first bonding metal layer on the first substrate, (b) providing a second substrate comprising successively: a semiconductor base substrate, a stack of a plurality of semiconductor epitaxial layers, a layer of SixGe1-x, with 0≤x≤1 being located at the surface of said stack opposite to the base substrate, and a second bonding metal layer, (c) bonding the first substrate and the second substrate through the first and second bonding metal layers at a temperature lower than or equal to 400° C., and (d) removing a part of the second substrate so as to transfer the layer of SixGe1-x on the first substrate using a selective etching process.

公开(公告)号：US10826459B2

公开(公告)日：2020-11-03

申请号：US15735477

申请日：2016-06-09

Applicant: Soitec

Inventor： Arnaud Castex ,  Daniel Delprat ,  Bernard Aspar ,  Ionut Radu

IPC: H03H9/02 ,  H03H3/10 ,  H01L41/312 ,  H01L41/08 ,  H01L41/313 ,  H01L41/47 ,  H03H3/04 ,  H01L41/332 ,  H01L41/337 ,  H03H9/64

Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

公开(公告)号：US20200161172A1

公开(公告)日：2020-05-21

申请号：US16685938

申请日：2019-11-15

Applicant: Soitec

Inventor： Marcel Broekaart ,  Ionut Radu ,  Chrystelle Lagahe Blanchard

IPC: H01L21/762 ,  H01L27/146 ,  H01L23/544

Abstract: The disclosure relates to a process for locating devices, the process comprising the following steps: a) providing a carrier substrate comprising: a device layer; and alignment marks; b) providing a donor substrate; c) forming a weak zone in the donor substrate, the weak zone delimiting a useful layer; d) assembling the donor substrate and the carrier substrate; and e) fracturing the donor substrate in the weak zone so as to transfer the useful layer to the device layer; wherein the alignment marks are placed in cavities formed in the device layer, the cavities having an aperture flush with the free surface of the device layer.

公开(公告)号：US09548237B2

公开(公告)日：2017-01-17

申请号：US14377738

申请日：2013-01-28

Applicant: Soitec

Inventor： Gweltaz Gaudin ,  Oleg Kononchuk ,  Ionut Radu

IPC: B32B7/04 ,  H01L21/762 ,  B32B9/04

CPC classification number: H01L21/76254 ,  B32B7/04 ,  B32B9/04 ,  B32B2457/14 ,  Y10T428/24802

Abstract: A method comprising the following steps: providing a support substrate and a donor substrate, forming an embrittlement region in the donor substrate so as to delimit a first portion and a second portion on either side of the embrittlement region, assembling the donor substrate on the support substrate, fracturing the donor substrate along the embrittlement region. In addition, the method comprises a step consisting of forming a compressive stress layer in the donor substrate so as to delimit a so-called confinement region interposed between the compressive stress layer and the embrittlement region.

Abstract translation: 一种包括以下步骤的方法：提供支撑衬底和供体衬底，在所述供体衬底中形成脆化区域，以限定所述脆化区域的任一侧上的第一部分和第二部分，将所述施主衬底组装在所述支撑体上 底物，沿着脆化区域压裂施主衬底。 此外，该方法包括在施主衬底中形成压应力层以限定介于压应力层和脆化区之间的所谓约束区的步骤。

公开(公告)号：US20140357093A1

公开(公告)日：2014-12-04

申请号：US14362208

申请日：2012-12-13

Applicant: Soitec

Inventor： Didier Landru ,  Carole David ,  Ionut Radu ,  Lucianna Capello ,  Yann Sinquin

IPC: H01L21/268 ,  H01L21/324

CPC classification number: H01L21/268 ,  H01L21/02354 ,  H01L21/2007 ,  H01L21/324 ,  H01L21/428

Abstract: The invention relates to a process for stabilizing a bonding interface, located within a structure for applications in the fields of electronics, optics and/or optoelectronics and that comprises an oxide layer buried between an active layer and a receiver substrate, the bonding interface having been obtained by molecular adhesion. In accordance with the invention, the process further comprises irradiating this structure with a light energy flux provided by a laser, so that the flux, directed toward the structure, is absorbed by the energy conversion layer and converted to heat in this layer, and in that this heat diffuses into the structure toward the bonding interface, so as to thus stabilize the bonding interface.

Abstract translation: 本发明涉及一种用于稳定接合界面的方法，该接合界面位于用于电子学，光学和/或光电子学领域的结构内，并且包括掩埋在有源层和接收器衬底之间的氧化物层，所述接合界面已被 通过分子粘附获得。 根据本发明，该方法还包括用激光提供的光能通量照射该结构，使得朝向结构的通量被能量转换层吸收并在该层中被转换成热 这种热量向结合界面扩散到结构中，从而稳定接合界面。

公开(公告)号：US08841742B2

公开(公告)日：2014-09-23

申请号：US13777231

申请日：2013-02-26

Applicant: Soitec

Inventor： Mariam Sadaka ,  Ionut Radu

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76254 ,  H01L29/06

Abstract: Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming recesses in the donor structure, implanting ions into the donor structure to form a generally planar, inhomogeneous weakened zone therein, and providing material within the recesses. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods.

Abstract translation: 将半导体材料层从第一施主结构转移到第二结构的方法包括在施主结构中形成凹陷，将离子注入施主结构中以在其中形成大致平坦的，不均匀的弱化区，并在凹陷内提供材料。 第一施主结构可以结合到第二结构，并且第一施主结构可以沿着大致平坦的弱化区断裂，留下半导体材料层与第二结构结合。 可以通过在半导体材料的转移层上形成有源器件结构来制造半导体器件。 使用所述方法制造半导体结构。

公开(公告)号：US20130175672A1

公开(公告)日：2013-07-11

申请号：US13777231

申请日：2013-02-26

Applicant: Soitec

Inventor： Mariam Sadaka ,  Ionut Radu

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76254 ,  H01L29/06

Abstract: Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming recesses in the donor structure, implanting ions into the donor structure to form a generally planar, inhomogeneous weakened zone therein, and providing material within the recesses. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods.

Abstract translation: 将半导体材料层从第一施主结构转移到第二结构的方法包括在施主结构中形成凹陷，将离子注入施主结构中以在其中形成大致平坦的，不均匀的弱化区，并在凹陷内提供材料。 第一施主结构可以结合到第二结构，并且第一施主结构可以沿着大致平坦的弱化区断裂，留下半导体材料层与第二结构结合。 可以通过在半导体材料的转移层上形成有源器件结构来制造半导体器件。 使用所述方法制造半导体结构。

公开(公告)号：US12198983B2

公开(公告)日：2025-01-14

申请号：US17756615

申请日：2020-10-26

Applicant: Soitec

Inventor： Ionut Radu ,  Hugo Biard ,  Christophe Maleville ,  Eric Guiot ,  Didier Landru

IPC: H01L21/78 ,  C23C16/32 ,  C30B25/20 ,  C30B29/36 ,  C30B31/22 ,  C30B33/10 ,  H01L21/02

Abstract: A method of producing a composite structure comprising a thin layer of monocrystalline silicon carbide arranged on a carrier substrate of silicon carbide comprises: a) a step of provision of an initial substrate of monocrystalline silicon carbide, b) a step of epitaxial growth of a donor layer of monocrystalline silicon carbide on the initial substrate, to form a donor substrate, c) a step of ion implantation of light species into the donor layer, to form a buried brittle plane delimiting the thin layer, d) a step of formation of a carrier substrate of silicon carbide on the free surface of the donor layer, comprising a deposition at a temperature of between 400° C. and 1100° C., e) a step of separation along the buried brittle plane, to form the composite structure and the remainder of the donor substrate, and f) a step of chemical-mechanical treatment(s) of the composite structure.