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1.发明授权Method and apparatus for spatially uniform electropolishing and electrolytic etching 失效用于空间均匀电解和电解蚀刻的方法和装置
公开(公告)号：US5096550A
公开(公告)日：1992-03-17
申请号：US597225
申请日：1990-10-15
CPC分类号： C25F7/00 , C25F3/02 , C25F3/16 , Y10S204/07
摘要： In an electropolishing or electrolytic etching apparatus the anode is separated from the cathode to prevent bubble transport to the anode and to produce a uniform current distribution at the anode by means of a solid nonconducting anode-cathode barrier. The anode extends into the top of the barrier and the cathode is outside the barrier. A virtual cathode hole formed in the bottom of the barrier below the level of the cathode permits current flow while preventing bubble transport. The anode is rotatable and oriented horizontally facing down. An extended anode is formed by mounting the workpiece in a holder which extends the electropolishing or etching area beyond the edge of the workpiece to reduce edge effects at the workpiece. A reference electrode controls cell voltage. Endpoint detection and current shut-off stop polishing. Spatially uniform polishing or etching can be rapidly performed.
摘要翻译： 在电解抛光或电解蚀刻装置中，阳极与阴极分离，以防止气泡传输到阳极，并通过固体非导电阳极 - 阴极屏障在阳极处产生均匀的电流分布。 阳极延伸到屏障的顶部，阴极在屏障外。 形成在阴极底部的阴极底部的虚拟阴极孔允许电流流动，同时防止气泡输送。 阳极可旋转并水平定向朝下。 扩展阳极通过将工件安装在将电解抛光或蚀刻区域延伸超过工件边缘的保持器中形成，以减少工件的边缘效应。 参考电极控制电池电压。 端点检测和电流切断停止抛光。 可以快速进行空间均匀的抛光或蚀刻。
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公开(公告)号：US6045678A
公开(公告)日：2000-04-04
申请号：US847088
申请日：1997-05-01
CPC分类号： C25D7/12
摘要： A process for fabricating a nanofilament field emission device. The process enables the formation of high aspect ratio, electroplated nanofilament structure devices for field emission displays wherein a via is formed in a dielectric layer and is self-aligned to a via in the gate metal structure on top of the dielectric layer. The desired diameter of the via in the dielectric layer is on the order of 50-200 nm, with an aspect ratio of 5-10. In one embodiment, after forming the via in the dielectric layer, the gate metal is passivated, after which a plating enhancement layer is deposited in the bottom of the via, where necessary. The nanofilament is then electroplated in the via, followed by removal of the gate passification layer, etch back of the dielectric, and sharpening of the nanofilament. A hard mask layer may be deposited on top of the gate metal and removed following electroplating of the nanofilament.
摘要翻译： 一种制造纳米丝场发射器件的方法。 该方法能够形成高纵横比，用于场致发射显示器的电镀纳米丝结构器件，其中通孔形成在电介质层中，并且与电介质层顶部的栅极金属结构中的通孔自对准。 电介质层中通孔的理想直径约为50-200nm，纵横比为5-10。 在一个实施例中，在电介质层中形成通孔之后，栅极金属被钝化，之后必要时在通孔的底部沉积电镀增强层。 然后将纳米丝电镀在通孔中，随后除去栅极钝化层，回蚀电介质，并使纳米丝的锐化。 硬掩模层可以沉积在栅极金属的顶部上，并在纳米丝的电镀之后去除。
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公开(公告)号：US5653019A
公开(公告)日：1997-08-05
申请号：US522471
申请日：1995-08-31
CPC分类号： H01L24/83 , H01L21/6835 , H01L24/19 , H01L24/24 , H01L24/29 , H01L24/82 , H01L2221/6835 , H01L2221/68359 , H01L2224/24051 , H01L2224/24226 , H01L2224/291 , H01L2224/29111 , H01L2224/2919 , H01L2224/82001 , H01L2224/83192 , H01L2224/8385 , H01L2924/01006 , H01L2924/01011 , H01L2924/01018 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/12042 , H01L2924/14 , H01L2924/19042 , Y10T29/49144
摘要： A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets.For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.
摘要翻译： 可修复的片对板互连过程，可解决多芯片模块中的成本和可测试性问题。 该工艺可以使用牺牲衬底技术进行，涉及激光加工。 该过程避免了以前的方法中遇到的固化/溶剂进化问题，以及解决先前的电镀问题和对圆角的要求。 对于可修复的高速芯片到板连接，传输线可以从芯片接合焊盘的芯片侧面形成，结束于芯片底部的鸥翼，用于随后的焊料。
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公开(公告)号：US5658832A
公开(公告)日：1997-08-19
申请号：US324052
申请日：1994-10-17
CPC分类号： H01J9/242 , H01J2329/00 , H01J2329/8625 , H01J2329/864
摘要： Spacers for applications such as field emission flat panel displays and vacuum microelectronics, and which involves the application of aerogel/xerogel technology to the formation of the spacer. In a preferred approach the method uses a mold and mold release agent wherein the gel precursor is a liquid which can be applied to the mold filling holes which expose the substrate (either the baseplate or the faceplate). A release agent is applied to the mold prior to precursor application to ease removal of the mold after formation of the dielectric spacer. The shrinkage of the gel during solvent extraction also improves mold removal. The final spacer material is a good dielectric, such as silica, secured to the substrate.
摘要翻译： 用于场致发射平板显示器和真空微电子等应用的间隔器，其涉及将气凝胶/干凝胶技术应用于间隔物的形成。 在优选的方法中，该方法使用模具和脱模剂，其中凝胶前体是可以施加到暴露基底（基板或面板）的模具填充孔的液体。 在前体施用之前将脱模剂施加到模具以便在形成介电隔离物之后容易地移除模具。 溶剂萃取过程中凝胶的收缩也提高了模具去除率。 最终的间隔材料是固定到基底上的良好的电介质，例如二氧化硅。
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公开(公告)号：US5256565A
公开(公告)日：1993-10-26
申请号：US348982
申请日：1989-05-08
IPC分类号： H01L21/28 , C23C18/31 , H01L21/3063 , H01L21/3205 , H01L21/321 , H01L21/768 , H01L21/465
CPC分类号： H01L21/7684 , H01L21/32115
摘要： In a process for fabricating planarized thin film metal interconnects for integrated circuit structures, a planarized metal layer is etched back to the underlying dielectric layer by electropolishing, ion milling or other procedure. Electropolishing reduces processing time from hours to minutes and allows batch processing of multiple wafers. The etched back planarized thin film interconnect is flush with the dielectric layer.
摘要翻译： 在用于制造用于集成电路结构的平坦化薄膜金属互连件的工艺中，通过电抛光，离子铣削或其它程序将平坦化金属层回蚀刻到下面的介电层。 电抛光将处理时间从几小时缩短到几分钟，并允许批量处理多个晶圆。 蚀刻后的平坦化薄膜互连与电介质层齐平。
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公开(公告)号：US06417754B1
公开(公告)日：2002-07-09
申请号：US09206498
申请日：1998-12-07
IPC分类号： H01F500
CPC分类号： H01F5/003 , H01F17/0033 , H01F41/046 , H01L23/5227 , H01L23/645 , H01L27/08 , H01L28/10 , H01L2924/0002 , Y10T29/4902 , H01L2924/00
摘要： A three-dimensional coil inductor is disclosed. The inductor includes a substrate; a set of lower electrically conductive traces positioned on the substrate; a core placed over the lower traces; a set of side electrically conductive traces laid on the core and the lower traces; and a set of upper electrically conductive traces attached to the side traces so as to form the inductor. Fabrication of the inductor includes the steps of forming a set of lower traces on a substrate; positioning a core over the lower traces; forming a set of side traces on the core; connecting the side traces to the lower traces; forming a set of upper traces on the core; and connecting the upper traces to the side traces so as to form a coil structure.
摘要翻译： 公开了一种三维线圈电感器。 电感器包括衬底; 位于基板上的一组下部导电迹线; 放置在较低轨迹上的核心; 一组侧导电迹线放置在芯和下迹线上; 以及一组连接到侧迹的上部导电迹线，以形成电感器。 电感器的制造包括在衬底上形成一组下部迹线的步骤; 将芯定位在下轨道上; 在芯上形成一组侧面迹线; 将侧面迹线连接到下部迹线; 在芯上形成一组上部迹线; 并且将上部迹线连接到侧面迹线以形成线圈结构。
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公开(公告)号：US5891321A
公开(公告)日：1999-04-06
申请号：US847087
申请日：1997-05-01
申请人： Anthony F. Bernhardt
发明人： Anthony F. Bernhardt
摘要： A method for sharpening field emitter tips by electroetching/polishing. In gated field emitters, it is very important to initiate electron emission at the lowest possible voltage and thus the composition of the emitter and the gate, as well as the emitter-gate structure, are important factors. This method of sharpening the emitter tips uses the grid as a counter electrode in electroetching of the emitters, which can produce extremely sharp emitter tips as well as remove asperities and other imperfections in the emitters, each in relation to the specific grid hole in which it resides. This has the effect of making emission more uniform among the emitters as well as lowering the turn-on voltage.
摘要翻译： 通过电蚀/抛光来锐化场发射器尖端的方法。 在选通场发射器中，以最低可能的电压启动电子发射是非常重要的，因此发射极和栅极以及发射极 - 栅极结构的组成是重要的因素。 这种锐化发射极尖端的方法使用栅极作为电极在发射极的电极中的对电极，其可以产生非常尖锐的发射极尖端以及去除发射体中的凹凸和其它缺陷，每个发射极相对于其中的特定栅格孔 居住。 这具有使发射体之间更均匀的发射以及降低导通电压的效果。
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公开(公告)号：US4551684A
公开(公告)日：1985-11-05
申请号：US463713
申请日：1983-02-04
申请人： Anthony F. Bernhardt
发明人： Anthony F. Bernhardt
CPC分类号： H01S3/2308 , H01S3/08 , H01S3/083 , H01S2301/02 , H01S3/0805 , H01S3/235
摘要： Amplified spontaneous emission is substantially reduced in a novel optical amplifier wherein the gain medium is disposed within a converging region of the coherent signal, which converging region terminates in a waist at or near a limiting stop or saturable absorber. In contrast to the converging coherent signal flux, the amplified spontaneous emission flux is nonconverging and therefore most of the latter is removed by a spatial filter or saturable absorber.
摘要翻译： 在新型光学放大器中，放大的自发发射显着减少，其中增益介质设置在相干信号的会聚区域内，该会聚区域终止于限制停止或可饱和吸收体处或附近的腰部。 与收敛的相干信号通量相反，放大的自发发射通量是非融合的，因此后者的大部分被空间滤波器或可饱和吸收器去除。
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公开(公告)号：US5241450A
公开(公告)日：1993-08-31
申请号：US850642
申请日：1992-03-13
IPC分类号： H01L25/00 , H01L23/473 , H01L23/52 , H01L23/538 , H01L25/10 , H05K7/02
CPC分类号： H01L23/473 , H01L23/5385 , H01L24/24 , H05K7/023 , H01L25/105 , H01L2924/01322 , H01L2924/12042 , H01L2924/14 , H01L2924/15787 , H01L2924/1627 , H01L2924/3011 , H01L2924/3511
摘要： A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow "dummy chips" are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned o the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.
摘要翻译： 多个多芯片模块通过销售凸块连接到例如周边的三个侧面上的相邻模块而堆叠并围绕周边粘合。 根据芯片组的特定设计考虑，第四面可以用于冷却剂分配，更多互连结构或其他特征。 多芯片模块包括具有形成在第一主表面上的平坦化互连结构的电路板和结合到平坦化互连表面的集成电路芯片。 在每个电路板的周围，长而窄的“虚拟芯片”被结合到成品电路板上以形成周边壁。 墙壁高于电路板上的任何芯片，使得上述板的平坦背面仅接触周边壁。 模块到模块互连以相同的方式在板的侧面和周边壁上被激光图案化，并且同时该芯片对板互连可以是激光图案化的。
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公开(公告)号：US4063090A
公开(公告)日：1977-12-13
申请号：US519706
申请日：1974-10-30
申请人： Anthony F. Bernhardt
发明人： Anthony F. Bernhardt
CPC分类号： B01D59/34
摘要： In the method of separating isotopes wherein a desired isotope species is selectively deflected out of a beam of mixed isotopes by irradiating the beam with a directed beam of light of narrowly defined frequency which is selectively absorbed by the desired species, the improvement comprising irradiating the deflected beam with light from other light sources whose frequencies are selected to cause the depopulation of any metastable excited states.
摘要翻译： 在分离同位素的方法中，其中期望的同位素种类被选择性地从混合同位素束偏转出来，通过用所需物种选择性吸收的具有限定频率的定向频率的定向光束照射光束，改进之处是照射偏转的 光束来自其他光源的光，其频率被选择以导致任何亚稳态激发态的衰减。
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