公开(公告)号：US11444173B2

公开(公告)日：2022-09-13

申请号：US15797973

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku Shen ,  Jin-Mu Yin ,  Tsung-Chieh Hsiao ,  Chia-Lin Chuang ,  Li-Zhen Yu ,  Dian-Hau Chen ,  Shih-Wei Wang ,  De-Wei Yu ,  Chien-Hao Chen ,  Bo-Cyuan Lu ,  Jr-Hung Li ,  Chi-On Chui ,  Min-Hsiu Hung ,  Hung-Yi Huang ,  Chun-Cheng Chou ,  Ying-Liang Chuang ,  Yen-Chun Huang ,  Chih-Tang Peng ,  Cheng-Po Chau ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/311 ,  H01L29/78 ,  H01L21/768 ,  H01L21/3065 ,  H01L29/45 ,  H01L29/08 ,  H01L29/165

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.

公开(公告)号：US11289583B2

公开(公告)日：2022-03-29

申请号：US16453799

申请日：2019-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Chi-On Chui ,  Kai-Hsuan Lee ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes providing a substrate; forming mandrel patterns over the substrate; forming sacrificial patterns in openings between the mandrel patterns; removing the mandrel patterns; forming a dielectric layer in openings between the sacrificial patterns; removing the sacrificial patterns, resulting in a plurality of trenches; and forming a gate stack in each of the plurality of trenches.

公开(公告)号：US11233130B2

公开(公告)日：2022-01-25

申请号：US16798440

申请日：2020-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi-On Chui

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of semiconductor nanosheets, a bottom dielectric layer, and a gate stack. The substrate includes at least one fin. The plurality of semiconductor nanosheets are stacked on the at least one fin. The bottom dielectric layer is disposed between the at least one fin and the plurality of semiconductor nanosheets. The gate stack wraps the plurality of semiconductor nanosheets.

公开(公告)号：US11107897B2

公开(公告)日：2021-08-31

申请号：US16524137

申请日：2019-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Hao Chang ,  Cheng-Hao Hou ,  Kuei-Lun Lin ,  Kun-Yu Lee ,  Xiong-Fei Yu ,  Chi-On Chui

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28

Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate structure over the substrate. The gate structure includes a high-k layer over the substrate, a shielding layer over the high-k layer, and an N-type work function metal layer over the shielding layer. In some embodiments, the shielding layer has a dielectric constant less than a dielectric constant of the high-k layer.

公开(公告)号：US10367078B2

公开(公告)日：2019-07-30

申请号：US15876223

申请日：2018-01-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yuan Chang ,  Che-Hao Chang ,  Cheng-Hao Hou ,  Kuei-Lun Lin ,  Kun-Yu Lee ,  Xiong-Fei Yu ,  Chi-On Chui

IPC: H01L29/40 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28

Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate structure over the substrate. The gate structure includes a high-k layer over the substrate, a shielding layer over the high-k layer, and an N-type work function metal layer over the shielding layer. In some embodiments, the shielding layer has a dielectric constant less than a dielectric constant of the high-k layer.

公开(公告)号：US11417748B2

公开(公告)日：2022-08-16

申请号：US16735660

申请日：2020-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Bi-Fen Wu ,  Chi-On Chui

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device including a gate structure disposed on a substrate is provided. The gate structure includes a work function setting layer and a work function tuning layer sequentially disposed on substrate. The work function tuning layer is in contact with an interface surface positioned between the work function setting layer and the work function tuning layer, and a material of the interface surface is different from the work function setting layer.

公开(公告)号：US11316047B2

公开(公告)日：2022-04-26

申请号：US16662922

申请日：2019-10-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Ting Ko ,  Bo-Cyuan Lu ,  Jr-Hung Li ,  Chi-On Chui

IPC: H01L21/768 ,  H01L21/02 ,  H01L29/78 ,  H01L23/535 ,  H01L29/04 ,  H01L29/165 ,  H01L29/08 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/51

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes forming a gate structure over the substrate. The gate structure has a first sidewall. The method includes forming a spacer element over the first sidewall of the gate structure. The method includes forming a source/drain portion adjacent to the spacer element and the gate structure. The source/drain portion has a first top surface. The method includes depositing an etch stop layer over the first top surface of the source/drain portion. The etch stop layer is made of nitride. The method includes forming a dielectric layer over the etch stop layer. The dielectric layer has a second sidewall and a bottom surface, the etch stop layer is in direct contact with the bottom surface, and the spacer element is in direct contact with the second sidewall.

公开(公告)号：US11164868B2

公开(公告)日：2021-11-02

申请号：US16777831

申请日：2020-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Weng Chang ,  Chi-On Chui

IPC: H01L27/088

Abstract: A semiconductor device may include a substrate, a first transistor disposed on the substrate, and a second transistor disposed on the substrate. The first gate structure of the first transistor may include a first high-k layer, a first capping layer and a first work function layer sequentially disposed on the substrate. A material of the first work function layer includes Ta. The second transistor includes a second gate structure. The second gate structure includes a second high-k layer, a second capping layer and a second work function layer sequentially disposed on the substrate. The first capping layer and the second capping layer are formed of the same layer, and a material of the second work function layer is different from the material of the first work function layer.

公开(公告)号：US20210134971A1

公开(公告)日：2021-05-06

申请号：US16735660

申请日：2020-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Bi-Fen Wu ,  Chi-On Chui

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/8234

Abstract: A semiconductor device including a gate structure disposed on a substrate is provided. The gate structure includes a work function setting layer and a work function tuning layer sequentially disposed on substrate. The work function tuning layer is in contact with an interface surface positioned between the work function setting layer and the work function tuning layer, and a material of the interface surface is different from the work function setting layer.

公开(公告)号：US20210091077A1

公开(公告)日：2021-03-25

申请号：US16777831

申请日：2020-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Weng Chang ,  Chi-On Chui

IPC: H01L27/088 ,  H01L27/092 ,  H01L21/8234

Abstract: A semiconductor device may include a substrate, a first transistor disposed on the substrate, and a second transistor disposed on the substrate. The first gate structure of the first transistor may include a first high-k layer, a first capping layer and a first work function layer sequentially disposed on the substrate, wherein a material of the first work function layer includes Ta. The second transistor includes a second gate structure. The second gate structure includes a second high-k layer, a second capping layer and a second work function layer sequentially disposed on the substrate, wherein the first capping layer and the second capping layer are formed of the same layer, and a material of the second work function layer is different from the material of the first work function layer.