公开(公告)号：US12300496B2

公开(公告)日：2025-05-13

申请号：US18359735

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Chou ,  Kuan-Yu Yeh ,  Wei-Yip Loh ,  Hung-Hsu Chen ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/285 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H10D64/62

Abstract: The present disclosure provides a method to enlarge the process window for forming a source/drain contact. The method may include receiving a workpiece that includes a source/drain feature exposed in a source/drain opening defined between two gate structures, conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature, anisotropically etching the dielectric layer to expose the source/drain feature, performing an implantation process to the dielectric layer, and after the performing of the implantation process, performing a pre-clean process to the workpiece. The implantation process includes a non-zero tilt angle.

公开(公告)号：US20250098206A1

公开(公告)日：2025-03-20

申请号：US18968754

申请日：2024-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Chou ,  Yi-Syuan Siao ,  Su-Hao Liu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a source/drain region, forming a dielectric layer over the source/drain region, and etching the dielectric layer to form a contact opening. The source/drain region is exposed to the contact opening. The method further includes depositing a dielectric spacer layer extending into the contact opening, etching the dielectric spacer layer to form a contact spacer in the contact opening, implanting a dopant into the source/drain region through the contact opening after the dielectric spacer layer is deposited, and forming a contact plug to fill the contact opening.

公开(公告)号：US12249592B2

公开(公告)日：2025-03-11

申请号：US17648236

申请日：2022-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-De Chen ,  Cheng-I Chu ,  Yun Chen Teng ,  Chen-Fong Tsai ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/00 ,  H01L21/66 ,  H01L23/00

Abstract: A method includes placing a first wafer on a first wafer stage, placing a second wafer on a second wafer stage, and pushing a center portion of the first wafer to contact the second wafer. A bonding wave propagates from the center portion to edge portions of the first wafer and the second wafer. When the bonding wave propagates from the center portion to the edge portions of the first wafer and the second wafer, a stage gap between the top wafer stage and the bottom wafer stage is reduced.

公开(公告)号：US12237211B2

公开(公告)日：2025-02-25

申请号：US17377667

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh Chang ,  Chen-Fong Tsai ,  Yun Chen Teng ,  Han-De Chen ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L21/67

Abstract: A method of forming a semiconductor device includes mounting a bottom wafer on a bottom chuck and mounting a top wafer on a top chuck, wherein one of the bottom chuck and the top chuck has a gasket. The top chuck is moved towards the bottom chuck. The gasket forms a sealed region between the bottom chuck and the top chuck around the top wafer and the bottom wafer. An ambient pressure in the sealed region is adjusted. The top wafer is bonded to the bottom wafer.

公开(公告)号：US12211901B2

公开(公告)日：2025-01-28

申请号：US17869321

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bau-Ming Wang ,  Che-Fu Chiu ,  Chun-Feng Nieh ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/10 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L21/74 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device may include a semiconductor fin, a source/drain region extending from the semiconductor fin, and a gate electrode over the semiconductor fin. The semiconductor fin may include a first well and a channel region over the first well. The first well may have a first dopant at a first dopant concentration and the channel region may have the first dopant at a second dopant concentration smaller than the first dopant concentration. The first dopant concentration may be in range from 1017 atoms/cm3 to 1019 atoms/cm3.

公开(公告)号：US20240321751A1

公开(公告)日：2024-09-26

申请号：US18654111

申请日：2024-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Chun-Hsien Huang ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L23/532 ,  H01L21/3215 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53242 ,  H01L21/3215 ,  H01L21/76883 ,  H01L23/5226

Abstract: A semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants. The dopants are bonded to the noble metal material.

公开(公告)号：US20240266285A1

公开(公告)日：2024-08-08

申请号：US18639595

申请日：2024-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Fong Tsai ,  Cheng-I Chu ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L23/528 ,  H01L23/367 ,  H01L23/46 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L23/528 ,  H01L23/3672 ,  H01L23/46 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/0665 ,  H01L29/42392

Abstract: Semiconductor devices having improved heat dissipation and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including front-side conductive lines; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including backside conductive lines, the backside conductive lines having line widths greater than line widths of the front-side conductive lines; and a first heat dissipation substrate coupled to the backside interconnect structure.

公开(公告)号：US20240266229A1

公开(公告)日：2024-08-08

申请号：US18625377

申请日：2024-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Po-Kang Ho ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762 ,  H01L27/092

CPC classification number: H01L21/823878 ,  H01L21/02164 ,  H01L21/02332 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/823821 ,  H01L27/0924

Abstract: A device includes a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a dielectric fin over the substrate, a first isolation region between the first semiconductor fin and the dielectric fin, and a second isolation region between the first semiconductor fin and the second semiconductor fin. The first semiconductor fin is disposed between the second semiconductor fin and the dielectric fin. The first isolation region has a first concentration of an impurity. The second isolation region has a second concentration of the impurity. The second concentration is less than the first concentration. A top surface of the second isolation region is disposed closer to the substrate than a top surface of the first isolation region.

公开(公告)号：US20240153786A1

公开(公告)日：2024-05-09

申请号：US18410100

申请日：2024-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huicheng Chang ,  Jyh-Cherng Sheu ,  Chen-Fong Tsai ,  Yun Chen Teng ,  Han-De Chen ,  Yee-Chia Yeo

IPC: H01L21/56 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L25/0652 ,  H01L25/50

Abstract: A method includes bonding a package component to a composite carrier. The composite carrier includes a base carrier and an absorption layer, and the absorption layer is between the base carrier and the package component. A laser beam is projected onto the composite carrier. The laser beam penetrates through the base carrier to ablate the absorption layer. The base carrier may then be separated from the package component.

公开(公告)号：US11978677B2

公开(公告)日：2024-05-07

申请号：US17459164

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chih-Kai Yang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/66 ,  H01J37/20 ,  H01J37/22 ,  H01J37/304 ,  H01J37/317 ,  H01L21/265 ,  H01L23/544

CPC classification number: H01L22/20 ,  H01J37/20 ,  H01J37/22 ,  H01J37/3045 ,  H01J37/3171 ,  H01L21/265 ,  H01L23/544 ,  H01J2237/20214 ,  H01J2237/30438 ,  H01L2223/54426

Abstract: In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including alignment marks; measuring a position of the wafer by measuring positions of the alignment marks with one or more cameras; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.