公开(公告)号：US12294002B2

公开(公告)日：2025-05-06

申请号：US18664483

申请日：2024-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Hsien-Pin Hu ,  Yushun Lin ,  Heh-Chang Huang ,  Hsing-Kuo Hsia ,  Chih-Chieh Hung ,  Ying-Ching Shih ,  Chin-Fu Kao ,  Wen-Hsin Wei ,  Li-Chung Kuo ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L25/00 ,  H01L21/48 ,  H01L23/24 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

公开(公告)号：US11990429B2

公开(公告)日：2024-05-21

申请号：US17994548

申请日：2022-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih ,  Kung-Chen Yeh ,  Li-Chung Kuo ,  Pu Wang ,  Szu-Wei Lu

IPC: H01L23/00 ,  H01L21/3105 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L23/562 ,  H01L21/31053 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49827 ,  H01L25/18 ,  H01L25/50

Abstract: A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.

公开(公告)号：US11728254B2

公开(公告)日：2023-08-15

申请号：US16881211

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Hsien-Pin Hu ,  Sao-Ling Chiu ,  Wen-Hsin Wei ,  Ping-Kang Huang ,  Chih-Ta Shen ,  Szu-Wei Lu ,  Ying-Ching Shih ,  Wen-Chih Chiou ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49861 ,  H01L24/13 ,  H01L23/5385 ,  H01L2224/023 ,  H01L2225/107

Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

公开(公告)号：US11557568B2

公开(公告)日：2023-01-17

申请号：US16801171

申请日：2020-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01L25/00 ,  H01L21/48 ,  H01L23/48

Abstract: A package includes at least one memory component and an insulating encapsulation. The at least one memory component includes a stacked memory structure and a plurality of conductive posts. The stacked memory structure is laterally encapsulated in a molding compound. The conductive posts are disposed on an upper surface of the stacked memory structure. The upper surface of the stacked memory structure is exposed from the molding compound. The insulating encapsulation encapsulates the at least one memory component. The top surfaces of the conductive posts are exposed form the insulating encapsulation. A material of the molding compound is different a material of the insulating encapsulation.

公开(公告)号：US11145562B2

公开(公告)日：2021-10-12

申请号：US16721829

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hua Chang ,  Chih-Wei Wu ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure includes an interposer, a die and a conductive terminal. The interposer includes an encapsulant substrate, a through via and an interconnection structure. The through via is embedded in the encapsulant substrate. The interconnection structure is disposed on a first side of the encapsulant substrate and electrically connected to the through via. The die is electrically bonded to the interposer and disposed over the interconnection structure and the first side of the encapsulant substrate. The conductive terminal is disposed on a second side of the encapsulant substrate vertically opposite to the first side, and electrically connected to the interposer and the die.

公开(公告)号：US20210202436A1

公开(公告)日：2021-07-01

申请号：US16888868

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kung-Chen Yeh ,  Szu-Wei Lu ,  Tsung-Fu Tsai ,  Ying-Ching Shih

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/065 ,  H01L21/268 ,  H01L21/304

Abstract: A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.

公开(公告)号：US20210098421A1

公开(公告)日：2021-04-01

申请号：US16805865

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/768

Abstract: A package component for carrying a device package and an insulating layer thereon includes a molding layer, first and second redistribution structures disposed on two opposite sides of the molding layer, a semiconductor die, and a through interlayer via (TIV). A hardness of the molding layer is greater than that of the insulating layer that covers the device package. The device package is mounted on the second redistribution structure, and the insulating layer is disposed on the second redistribution structure opposite to the molding layer. The semiconductor die is embedded in the molding layer and electrically coupled to the device package through the second redistribution structure. The TIV penetrates through the molding layer to connect the first and the second redistribution structure. An electronic device and a manufacturing method thereof are also provided.

公开(公告)号：US20210082894A1

公开(公告)日：2021-03-18

申请号：US16572619

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Weiming Chris Chen ,  Chi-Hsi Wu ,  Chih-Wei Wu ,  Kuo-Chiang Ting ,  Szu-Wei Lu ,  Shang-Yun Hou ,  Ying-Ching Shih ,  Hsien-Ju Tsou ,  Cheng-Chieh Li

IPC: H01L25/18 ,  H01L23/367 ,  H01L25/00 ,  H01L23/00 ,  H01L21/82 ,  H01L23/48 ,  H01L21/56

Abstract: A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.

公开(公告)号：US10756058B2

公开(公告)日：2020-08-25

申请号：US16116892

申请日：2018-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Ching Shih ,  Chih-Wei Wu ,  Szu-Wei Lu

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L21/56

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first chip, a second chip, self-aligned structures, a bridge structure, and an insulating encapsulant. The first chip has a first rear surface opposite to a first active surface. The second chip is disposed beside the first chip and has a second rear surface opposite to a second active surface. The self-aligned structures are disposed on the first rear surface of the first chip and the second rear surface of the second chip. The bridge structure is electrically connected to the first chip and the second chip. The insulating encapsulant covers at least the side surfaces of the first and second chips, a side surface of the semiconductor substrate, and the side surfaces of the self-aligned structures.

公开(公告)号：US20200035622A1

公开(公告)日：2020-01-30

申请号：US16595741

申请日：2019-10-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/14 ,  H01L23/48 ,  H01L23/498

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure has a first conductive layer on a first substrate and a second conductive layer on a second substrate. A bonding structure is disposed between the first conductive layer and the second conductive layer. A support structure is disposed between the first substrate and the second substrate. A passivation layer covers a bottom surface of the first conductive layer and has a lower surface facing an uppermost surface of the support structure.