公开(公告)号：US06194776B1

公开(公告)日：2001-02-27

申请号：US08850111

申请日：1997-05-01

申请人： Teruhiko Amano ,  Masaki Tsukude

发明人： Teruhiko Amano ,  Masaki Tsukude

IPC分类号： H01L2900

CPC分类号： H01L21/823493 ,  H01L21/761 ,  H01L29/1079 ,  H01L29/1087 ,  Y10S257/901

摘要： A semiconductor circuit device having a triple-well structure wherein a predetermined potential level is supplied to a top well without a contact region formed in the top well is disclosed. In an N-type ion implantation step for forming an N-type well region (1) in a P-type semiconductor substrate (5), a mask of a predetermined configuration is used so that ions are not implanted into a region of a portion which is to serve as a bottom portion (1B) of the well region (1). Then, the N-type well region (1) is formed which is shaped such that a portion (6) having P-type properties remains partially in the bottom portion (1B). The P-type portion (6) establishes electrical connection between a P-type well region (2) and the semiconductor substrate (5) to permit the potential applied to a contact region (4) to be supplied to the well region (2) therethrough. The portion (6) may include a plurality of portions (6) which allow uniform potential supply. This structure may be applied to basic cells of a memory cell array block.

摘要翻译： 公开了一种具有三阱结构的半导体电路器件，其中将预定电位电平提供给顶部阱，而不形成在顶部阱中的接触区域。 在用于在P型半导体衬底（5）中形成N型阱区（1）的N型离子注入步骤中，使用预定构造的掩模，使得离子不被注入到部分的区域中 其用作井区（1）的底部（1B）。 然后，形成N型阱区域（1），其形状使得具有P型特性的部分（6）部分地保留在底部（1B）中。 P型部分（6）建立P型阱区（2）和半导体衬底（5）之间的电连接，以允许施加到接触区（4）的电势被提供给阱区（2） 通过。 部分（6）可以包括允许均匀电势供应的多个部分（6）。 该结构可以应用于存储单元阵列块的基本单元。

公开(公告)号：US5894448A

公开(公告)日：1999-04-13

申请号：US944642

申请日：1997-10-06

申请人： Teruhiko Amano ,  Masaki Tsukude

发明人： Teruhiko Amano ,  Masaki Tsukude

IPC分类号： G11C11/41 ,  G11C5/02 ,  G11C5/06 ,  G11C11/401 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C5/063 ,  G11C5/025

摘要： Memory mats provided in four regions formed by dividing a semiconductor chip are each further divided into a plurality of memory arrays along the longer side direction of the chip, row related circuits are provided between the memory arrays along the shorter side direction of the chip, and column decoders are provided along the longer side direction of the chip. An internal control signal from a master control circuit in the central part of the chip is transmitted in the central region with respect to the shorter side direction of the chip, buffer circuits are provided to an internal control signal transmission bus, and an internal signal is transmitted to the row related circuit and the column decoder by the buffer circuit. The length of the signal line to drive is shortened, and therefore the signal can be transmitted at a high speed, thus enabling high speed accessing. Thus, signal propagation delay can be reduced even if the chip size increases.

摘要翻译： 设置在通过划分半导体芯片形成的四个区域中的存储器垫每个被进一步沿着芯片的较长边方向分成多个存储器阵列，行相关电路沿着芯片的较短边方向设置在存储器阵列之间，并且 沿芯片的长边方向设置列解码器。 来自芯片中心的主控制电路的内部控制信号相对于芯片的短边方向在中央区域传输，缓冲电路被提供给内部控制信号传输总线，内部信号为 通过缓冲电路传输到行相关电路和列解码器。 要驱动的信号线的长度被缩短，因此可以高速传输信号，从而实现高速访问。 因此，即使芯片尺寸增加，也可以降低信号传播延迟。

公开(公告)号：US06707735B2

公开(公告)日：2004-03-16

申请号：US10120445

申请日：2002-04-12

申请人： Ryu Makabe ,  Masaki Tsukude ,  Hirotoshi Sato

发明人： Ryu Makabe ,  Masaki Tsukude ,  Hirotoshi Sato

IPC分类号： G11C700

CPC分类号： G11C29/46

摘要： When address signal bits and/or data bits in a predetermined pattern are accessed a predetermined number of times successively, a test mode can be set. By using address signal bits and/or data bits as a test command for designating a test content, a test content is specified. A semiconductor memory device with an interface compatible with an interface of a normal static random access memory is provided.

摘要翻译： 当预定模式的地址信号位和/或数据位连续访问预定次数时，可以设置测试模式。 通过使用地址信号位和/或数据位作为用于指定测试内容的测试命令，指定测试内容。 提供具有与普通静态随机存取存储器的接口兼容的接口的半导体存储器件。

公开(公告)号：US06590823B2

公开(公告)日：2003-07-08

申请号：US09988172

申请日：2001-11-19

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： A refresh circuit performs directive operation for the execution of refresh operation in response to a cycle signal cyclically output from a timer circuit provided in a command-signal activating circuit. To execute testing, a stop signal generated in response to an external signal is activated, the activated stop signal is input to an AND gate, and the cycle signal is thereby invalidated. This causes the refresh operation to terminate, thereby enabling this semiconductor memory device to refresh characteristic testing to be performed.

公开(公告)号：US06556485B2

公开(公告)日：2003-04-29

申请号：US09972242

申请日：2001-10-09

申请人： Tadayuki Shimizu ,  Hirotoshi Sato ,  Masaki Tsukude

发明人： Tadayuki Shimizu ,  Hirotoshi Sato ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C7/1051

摘要： An output buffer includes first current driving units connected in parallel between a power-supply voltage and an output node; second current driving units connected in parallel between a ground voltage and an output node; a plurality of operation selection circuits setting the respective first and second current driving units to be in either activated or inactivated state in a non-volatile manner; first signal transmission circuits arranged respectively corresponding to the first current driving circuits and each transmitting the level of output data with a similar first propagation time period; and second signal transmission circuits arranged respectively corresponding to the second current driving units and each transmitting the level of the output data with a similar second propagation time period.

公开(公告)号：US06341098B2

公开(公告)日：2002-01-22

申请号：US09846223

申请日：2001-05-02

申请人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

发明人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C5/14 ,  G11C5/147 ,  G11C7/22 ,  G11C8/08 ,  G11C11/4074 ,  H03K19/0016

摘要： A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

摘要翻译： 分别提供电压VCL1和VSL1的可变阻抗电源线和可变阻抗接地线在待机周期和行相关信号设定周期中被设置为低阻抗状态，并且在 列电路有效时间段。 可变阻抗电源线和可变阻抗地线供电电压VCL2和VSL2分别在待机周期中被设置为高阻抗状态，并且在有效周期和行相关信号复位时间段中被设置为低阻抗状态。 根据待机周期和激活周期中的输出信号的逻辑电平，变频器作为电压VCL1和VSL2的工作电源电压或电压VCL2和VSL1运行。 因此，提供半导体存储器件，其中可以减少备用循环中的次阈值电流和有效周期中的有效直流电流。

公开(公告)号：US6150728A

公开(公告)日：2000-11-21

申请号：US854754

申请日：1997-05-12

申请人： Masaki Tsukude ,  Kazutami Arimoto

发明人： Masaki Tsukude ,  Kazutami Arimoto

IPC分类号： G11C11/401 ,  H01L21/321 ,  H01L21/60 ,  H01L21/8242 ,  H01L23/495 ,  H01L23/50 ,  H01L27/105 ,  H01L27/108 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L23/50 ,  H01L27/105 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01024 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01082

摘要： On a surface of a semiconductor chip having a longer side and a shorter side, a line of a plurality of first pads and a line of a plurality of second pads are arranged in the shape of a cross. Upon multibit expansion, increase in length of the longer side of semiconductor chip can be suppressed even though the number of pads is increased by additionally providing the second pad. In addition, there is no need to reduce the pitch between pads. Thus, a semiconductor memory device allowing multibit expansion is provided without an increase in size of the chip and the pad or reduction in pitches between pads and between pins.

摘要翻译： 在具有长边和短边的半导体芯片的表面上，多个第一焊盘的线和多个第二焊盘的线以交叉的形式布置。 在多位扩展时，即使通过另外设置第二焊盘来增加焊盘的数量，也可以抑制半导体芯片的长边的长度的增加。 此外，不需要减小垫之间的间距。 因此，提供了允许多位扩展的半导体存储器件，而不增加芯片和焊盘的尺寸，或者减小焊盘之间和引脚之间的间距。

公开(公告)号：US6038183A

公开(公告)日：2000-03-14

申请号：US288019

申请日：1999-04-08

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G01R31/28 ,  G01R31/30 ,  G11C5/00 ,  G11C11/401 ,  G11C11/407 ,  G11C29/06 ,  G11C7/00

CPC分类号： G11C29/06 ,  G11C29/12005 ,  G11C29/26 ,  G11C29/34 ,  G11C29/50 ,  G11C5/00 ,  G11C11/401 ,  G11C2029/1202 ,  G11C2029/2602

摘要： Current is reduced in driving a word line in stress acceleration testing such as burn-in, and the time required for the stress acceleration testing is reduced. For an address signal applied from an address buffer, a predetermined internal address signal bit is degenerated and a remaining address signal bit is rendered valid in response to an activation of a stress acceleration mode designation signal to simultaneously drive a desired number of word lines of all word lines to selected state. Any number of word lines can be simultaneously selected and hence current flowing in driving word lines can be reduced in the stress acceleration mode. In the stress acceleration mode of operation, bit line voltage and cell plate voltage are changed, and a current required for driving a plurality of word lines into a selected state is limited.

摘要翻译： 压力加速度测试（如老化）中的字线驱动电流减少，应力加速测试所需的时间减少。 对于从地址缓冲器施加的地址信号，预定的内部地址信号位退化，并且剩余地址信号位响应于应力加速模式指定信号的激活而变为有效，以同时驱动所需数量的所有字线 字线到选定状态。 可以同时选择任何数量的字线，因此在应力加速模式中可以减少在驱动字线中流动的电流。 在应力加速操作模式中，位线电压和单元板电压发生变化，并且将多条字线驱动到选定状态所需的电流受到限制。

公开(公告)号：US6011428A

公开(公告)日：2000-01-04

申请号：US135650

申请日：1993-10-14

申请人： Masaki Tsukude ,  Masanori Hayashikoshi

发明人： Masaki Tsukude ,  Masanori Hayashikoshi

IPC分类号： G05F1/56 ,  G05F3/24 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  H03K5/003 ,  G05F1/10

CPC分类号： G05F3/245 ,  G05F3/24 ,  G11C5/147 ,  Y10S323/907

摘要： The level shifter circuit of an internal down converter includes a P channel MOS transistor constituting a resistance component, and a resistor constituting a resistance component. The temperature coefficient of resistance component is set larger than the temperature coefficient of resistance component so that the output voltage of level shifter circuit has a negative temperature characteristic. If a reference voltage generated by reference voltage generation circuit decreases when operating at a high temperature, the output voltage of level shifter circuit decreases as well. Thus, change in an internal voltage due to change in the operation temperature can be compensated.

摘要翻译： 内部下变频器的电平移位电路包括构成电阻分量的P沟道MOS晶体管和构成电阻分量的电阻。 电阻分量的温度系数设定为大于电阻分量的温度系数，使得电平移位器电路的输出电压具有负温度特性。 如果在高温工作时由参考电压产生电路产生的参考电压降低，则电平转换器电路的输出电压也会降低。 因此，可以补偿由于操作温度的变化引起的内部电压的变化。

公开(公告)号：US5987619A

公开(公告)日：1999-11-16

申请号：US947372

申请日：1997-10-08

申请人： Takeshi Hamamoto ,  Masaki Tsukude

发明人： Takeshi Hamamoto ,  Masaki Tsukude

IPC分类号： G11C11/407 ,  G06F1/10 ,  G11C11/409 ,  G06F1/04

CPC分类号： G06F1/10

摘要： An input signal phase compensation circuit having a monitor mode and a normal operation mode includes a mode switching circuit, a logic gate receiving an internal data signal, a delay circuit connected to the logic gate, and a phase comparator comparing, in the monitor mode, phases of a signal output from the delay circuit and a clock signal, and determining time for delaying an internal clock signal in a variable delay circuit so as to match phases of the both signals. In the normal operation mode, the time is fixed, and data is obtained at phase compensated timing.

摘要翻译： 具有监视模式和正常操作模式的输入信号相位补偿电路包括模式切换电路，接收内部数据信号的逻辑门，连接到逻辑门的延迟电路，以及在监视器模式下， 从延迟电路输出的信号的相位和时钟信号，以及确定用于延迟可变延迟电路中的内部时钟信号的时间，以便匹配两个信号的相位。 在正常工作模式下，时间是固定的，并且在相位补偿定时获得数据。