公开(公告)号：US11791198B2

公开(公告)日：2023-10-17

申请号：US17695119

申请日：2022-03-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hong Yang ,  Seetharaman Sridhar ,  Ya ping Chen ,  Fei Ma ,  Yunlong Liu ,  Sunglyong Kim

IPC: H01L21/762 ,  H01L21/763 ,  H01L29/66 ,  H01L21/308 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/76235 ,  H01L21/02164 ,  H01L21/308 ,  H01L21/324 ,  H01L21/763 ,  H01L21/76283 ,  H01L21/76286 ,  H01L29/66666

Abstract: A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

公开(公告)号：US11302568B2

公开(公告)日：2022-04-12

申请号：US16546499

申请日：2019-08-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hong Yang ,  Seetharaman Sridhar ,  Ya ping Chen ,  Fei Ma ,  Yunlong Liu ,  Sunglyong Kim

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/308 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324

Abstract: A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

公开(公告)号：US20200335589A1

公开(公告)日：2020-10-22

申请号：US16918130

申请日：2020-07-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ya ping Chen ,  Hong Yang ,  Peng Li ,  Seetharaman Sridhar ,  Yunlong Liu ,  Rui Liu

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including a semiconductor surface layer. A field plate (FP) includes a trench in the semiconductor surface layer filled with a single polysilicon layer positioned on at least one side of a power metal-oxide-semiconductor field effect transistor (power MOSFET). The power MOSFET includes a dielectric liner lining a sidewall of the trench under the polysilicon layer including a second dielectric liner on a first dielectric liner. An upper portion of the dielectric liner has a lower dielectric thickness as compared to a dielectric thickness on its lower portion. The single polysilicon layer extends continuously over the dielectric liner along both the lower portion and the upper portion. The power MOSFET includes a drain including a drain contact below a vertical drift region in the semiconductor surface layer, and a gate, body and a source above the vertical drift region.

公开(公告)号：US10720499B2

公开(公告)日：2020-07-21

申请号：US16042834

申请日：2018-07-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ya ping Chen ,  Hong Yang ,  Peng Li ,  Seetharaman Sridhar ,  Yunlong Liu ,  Rui Liu

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28

Abstract: A semiconductor device includes a substrate including a semiconductor surface layer. A field plate (FP) includes a trench in the semiconductor surface layer filled with a single polysilicon layer positioned on at least one side of a power metal-oxide-semiconductor field effect transistor (power MOSFET). The power MOSFET includes a dielectric liner lining a sidewall of the trench under the polysilicon layer including a second dielectric liner on a first dielectric liner. An upper portion of the dielectric liner has a lower dielectric thickness as compared to a dielectric thickness on its lower portion. The single polysilicon layer extends continuously over the dielectric liner along both the lower portion and the upper portion. The power MOSFET includes a drain including a drain contact below a vertical drift region in the semiconductor surface layer, and a gate, body and a source above the vertical drift region.

公开(公告)号：US20180061828A1

公开(公告)日：2018-03-01

申请号：US15790212

申请日：2017-10-23

Applicant: Texas Instruments Incorporated

Inventor： Yufei Xiong ,  Yunlong Liu ,  Hong Yang ,  Jianxin Liu

IPC: H01L27/088 ,  H01L29/94 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L49/02 ,  H01L27/06 ,  H01L23/528 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/265

CPC classification number: H01L27/088 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L23/5283 ,  H01L27/0629 ,  H01L28/40 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/66181 ,  H01L29/7827 ,  H01L29/945

Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

公开(公告)号：US20240113217A1

公开(公告)日：2024-04-04

申请号：US17958205

申请日：2022-09-30

Applicant: Texas Instruments Incorporated

Inventor： Hong Yang ,  Thomas Grebs ,  Yunlong Liu ,  Sunglyong Kim ,  Lindong Li ,  Peng Li ,  Seetharaman Sridhar ,  Yeguang Zhang ,  Sheng pin Yang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L21/823437 ,  H01L27/092 ,  H01L29/42368

Abstract: An integrated circuit includes first and second trenches in a semiconductor substrate and a semiconductor mesa between the first and second trenches. A source region having a first conductivity type and a body region having an opposite second conductivity type are located within the semiconductor mesa. A trench shield is located within the first trench, and a gate electrode is over the trench shield between first and second sidewalls of the first trench. A gate dielectric is on a sidewall of the first trench between the gate electrode and the body region, and a pre-metal dielectric (PMD) layer is over the gate electrode. A gate contact through the PMD layer touches the gate electrode between the first and second sidewalls, and a trench shield contact through the PMD layer touches the trench shield between the first and second sidewalls.

公开(公告)号：US11658241B2

公开(公告)日：2023-05-23

申请号：US16237210

申请日：2018-12-31

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  Seetharaman Sridhar ,  Hong Yang ,  Ya Ping Chen ,  Thomas Eugene Grebs

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L29/872 ,  H01L21/8234 ,  H01L29/40

CPC classification number: H01L29/7827 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/872

Abstract: An integrated circuit includes a trench gate MOSFET including MOSFET cells. Each MOSFET cell includes an active trench gate in an n-epitaxial layer oriented in a first direction with a polysilicon gate over a lower polysilicon portion. P-type body regions are between trench gates and are separated by an n-epitaxial region. N-type source regions are located over the p-type regions. A gate dielectric layer is between the polysilicon gates and the body regions. A metal-containing layer contacts the n-epitaxial region to provide an anode of an embedded Schottky diode. A dielectric layer over the n-epitaxial layer has metal contacts therethrough connecting to the n-type source regions, to the p-type body regions, and to the anode of the Schottky diode.

公开(公告)号：US11127852B2

公开(公告)日：2021-09-21

申请号：US16233643

申请日：2018-12-27

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  Seetharaman Sridhar ,  Hong Yang ,  Ya Ping Chen ,  Yunlong Liu ,  Fei Ma

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L21/225 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08

Abstract: A trench gate metal oxide semiconductor field effect transistor (MOSFET) device includes an epitaxial layer on a substrate both doped a first conductivity type. Active area trenches have polysilicon gates over a double shield field plate. A junction termination trench includes a single shield field plate in a junction termination area which encloses the active area that includes a retrograde dopant profile of the second conductivity type into the epitaxial layer in the junction termination area. Pbody regions of a second conductivity type are between active trenches and between the outermost active trench and the junction termination trench. Source regions of the first conductivity type are in the body regions between adjacent active trenches. Metal contacts are over contact apertures that extend through a pre-metal dielectric layer reaching the body region under the source region, the single shield field plate, and that couples together the polysilicon gates.

公开(公告)号：US10541326B2

公开(公告)日：2020-01-21

申请号：US15622869

申请日：2017-06-14

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Seetharaman Sridhar ,  Christopher Boguslaw Kocon ,  Simon John Molloy ,  Hong Yang

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches.

公开(公告)号：US10347626B2

公开(公告)日：2019-07-09

申请号：US15790212

申请日：2017-10-23

Applicant: Texas Instruments Incorporated

Inventor： Yufei Xiong ,  Yunlong Liu ,  Hong Yang ,  Jianxin Liu

IPC: H01L29/423 ,  H01L27/088 ,  H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/28 ,  H01L29/66 ,  H01L29/94 ,  H01L23/528 ,  H01L29/49 ,  H01L21/02 ,  H01L21/306 ,  H01L21/265

Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.