公开(公告)号：US09041204B2

公开(公告)日：2015-05-26

申请号：US13435702

申请日：2012-03-30

申请人： Tsung-Han Tsai ,  Jung-Chi Jeng ,  Yueh-Ching Chang ,  Volume Chien ,  Huang-Ta Huang ,  Chi-Cherng Jeng

发明人： Tsung-Han Tsai ,  Jung-Chi Jeng ,  Yueh-Ching Chang ,  Volume Chien ,  Huang-Ta Huang ,  Chi-Cherng Jeng

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L24/05 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L24/03 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/0508 ,  H01L2224/05083 ,  H01L2224/05085 ,  H01L2224/05086 ,  H01L2224/05087 ,  H01L2224/05088 ,  H01L2224/05096 ,  H01L2224/05098 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/3512 ,  H01L2924/35121

摘要： A bonding pad structure includes a substrate and a first conductive island formed in a first dielectric layer and disposed over the substrate. A first via array having a plurality of vias is formed in a second dielectric layer and disposed over the first conductive island. A second conductive island is formed in a third dielectric layer and disposed over the first via array. A bonding pad is disposed over the second conductive island. The first conductive island, the first via array, and the second conductive island are electrically connected to the bonding pad. The first via array is connected to no other conductive island in the first dielectric layer except the first conductive island. No other conductive island in the third dielectric layer is connected to the first via array except the second conductive island.

摘要翻译： 焊盘结构包括基板和形成在第一电介质层中并设置在基板上的第一导电岛。 具有多个通孔的第一通孔阵列形成在第二电介质层中并设置在第一导电岛上。 第二导电岛形成在第三电介质层中并且设置在第一通孔阵列上。 焊盘设置在第二导电岛上。 第一导电岛，第一通孔阵列和第二导电岛电连接到接合焊盘。 除了第一导电岛之外，第一通孔阵列连接到第一电介质层中没有其它导电岛。 除了第二导电岛之外，第三电介质层中没有其它导电岛连接到第一通孔阵列。

公开(公告)号：US06830981B2

公开(公告)日：2004-12-14

申请号：US10301715

申请日：2002-11-22

申请人： Chun-Tao Lee ,  Lin-Hung Shi ,  Chi-Cherng Jeng ,  Wen-Ti Lin ,  Wei-Su Chen

发明人： Chun-Tao Lee ,  Lin-Hung Shi ,  Chi-Cherng Jeng ,  Wen-Ti Lin ,  Wei-Su Chen

IPC分类号： H01L21331

CPC分类号： H01L51/057 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0504 ,  H01L51/0595 ,  Y10S977/843 ,  Y10S977/845

摘要： A vertical nanotube transistor and a process for fabricating the same. First, a source layer and a catalyst layer are successively formed on a substrate. A dielectric layer is formed on the catalyst layer and the substrate. Next, the dielectric layer is selectively removed to form a first dielectric mesa, a gate dielectric layer spaced apart from the first dielectric mesa by a first opening, and a second dielectric mesa spaced apart from the gate dielectric layer by a second opening. Next, a nanotube layer is formed in the first opening. Finally, a drain layer is formed on the nanotube layer and the first dielectric mesa, and a gate layer is formed in the second opening. The formation position of the nanotubes can be precisely controlled.

公开(公告)号：US09349902B2

公开(公告)日：2016-05-24

申请号：US13486833

申请日：2012-06-01

申请人： Shiu-Ko JangJian ,  Kei-Wei Chen ,  Chi-Cherng Jeng ,  Min Hao Hong

发明人： Shiu-Ko JangJian ,  Kei-Wei Chen ,  Chi-Cherng Jeng ,  Min Hao Hong

IPC分类号： H01L31/00 ,  H01L31/103 ,  H01L29/36 ,  H01L31/18

CPC分类号： H01L31/103 ,  H01L29/36 ,  H01L31/1037 ,  H01L31/18 ,  H01L31/1812 ,  Y02E10/50

摘要： System and method for processing a semiconductor device surface to reduce dark current and white pixel anomalies. An embodiment comprises a method applied to a semiconductor or photodiode device surface adjacent to a photosensitive region, and opposite a side having circuit structures for the device. A doped layer may optionally be created at a depth of less than about 10 nanometers below the surface of the substrate and may be doped with a boron concentration between about 1E13 and 1E16. An oxide may be created on the substrate using a temperature sufficient to reduce the surface roughness below a predetermined roughness threshold, and optionally at a temperature between about 300° C. and 500° C. and a thickness between about 1 nanometer and about 10 nanometers. A dielectric may then be created on the oxide, the dielectric having a refractive index greater than a predetermined refractive threshold, optionally at least about 2.0.

摘要翻译： 用于处理半导体器件表面以减少暗电流和白色像素异常的系统和方法。 一个实施例包括应用于与光敏区域相邻的半导体或光电二极管器件表面的方法，以及与该器件的电路结构相反的一侧。 掺杂层可以任选地在衬底表面下方小于约10纳米的深度处产生，并且可以掺杂在约1E13和1E16之间的硼浓度。 可以使用足以将表面粗糙度降低到预定粗糙度阈值以下且可选地在约300℃至500℃之间的温度和约1纳米至约10纳米的厚度的温度在基底上产生氧化物 。 然后可以在氧化物上产生电介质，电介质具有大于预定折射阈值的折射率，任选至少约2.0。

公开(公告)号：US20130249040A1

公开(公告)日：2013-09-26

申请号：US13429114

申请日：2012-03-23

申请人： Zhe-Ju Liu ,  Chi-Cherng Jeng ,  Kuo-Cheng Lee ,  Szu-Hung Yang ,  Po-Zen Chen ,  Chi-Chin Hsu

发明人： Zhe-Ju Liu ,  Chi-Cherng Jeng ,  Kuo-Cheng Lee ,  Szu-Hung Yang ,  Po-Zen Chen ,  Chi-Chin Hsu

IPC分类号： H01L27/146 ,  H01L31/18

CPC分类号： H01L27/14623 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464

摘要： A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed on the front side of the semiconductor substrate. A dielectric layer is disposed on the backside of the semiconductor substrate, wherein the dielectric layer is over a back surface of the semiconductor substrate. A metal shield is over the dielectric layer and overlapping the photo-sensitive device. A metal plug penetrates through the dielectric layer, wherein the metal plug electrically couples the metal shield to the semiconductor substrate.

摘要翻译： 一种器件包括具有正面和背面的半导体衬底。 光敏装置设置在半导体基板的正面上。 电介质层设置在半导体衬底的背面，其中电介质层在半导体衬底的背面之上。 金属屏蔽层在介电层上方并与光敏器件重叠。 金属插塞穿过电介质层，其中金属插头将金属屏蔽件电耦合到半导体衬底。

公开(公告)号：US20130320478A1

公开(公告)日：2013-12-05

申请号：US13486833

申请日：2012-06-01

申请人： Shiu-Ko JangJian ,  Kei-Wei Chen ,  Chi-Cherng Jeng ,  Min Hao Hong

发明人： Shiu-Ko JangJian ,  Kei-Wei Chen ,  Chi-Cherng Jeng ,  Min Hao Hong

IPC分类号： H01L31/103 ,  H01L29/36 ,  H01L31/18

CPC分类号： H01L31/103 ,  H01L29/36 ,  H01L31/1037 ,  H01L31/18 ,  H01L31/1812 ,  Y02E10/50

摘要： System and method for processing a semiconductor device surface to reduce dark current and white pixel anomalies. An embodiment comprises a method applied to a semiconductor or photodiode device surface adjacent to a photosensitive region, and opposite a side having circuit structures for the device. A doped layer may optionally be created at a depth of less than about 10 nanometers below the surface of the substrate and may be doped with a boron concentration between about 1E13 and 1E16. An oxide may be created on the substrate using a temperature sufficient to reduce the surface roughness below a predetermined roughness threshold, and optionally at a temperature between about 300° C. and 500° C. and a thickness between about 1 nanometer and about 10 nanometers. A dielectric may then be created on the oxide, the dielectric having a refractive index greater than a predetermined refractive threshold, optionally at least about 2.0.

摘要翻译： 用于处理半导体器件表面以减少暗电流和白色像素异常的系统和方法。 一个实施例包括应用于与光敏区域相邻的半导体或光电二极管器件表面的方法，以及与该器件的电路结构相反的一侧。 掺杂层可以任选地在衬底表面下方小于约10纳米的深度处产生，并且可以掺杂在约1E13和1E16之间的硼浓度。 可以使用足以将表面粗糙度降低到预定粗糙度阈值以下且可选地在约300℃至500℃之间的温度和约1纳米至约10纳米的厚度的温度在基底上产生氧化物 。 然后可以在氧化物上产生电介质，电介质具有大于预定折射阈值的折射率，任选至少约2.0。