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公开(公告)号：US20230320232A1
公开(公告)日：2023-10-05
申请号：US17723495
申请日：2022-04-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin
CPC classification number: H01L43/14 , H01L27/222 , H01L43/04 , H01L43/06
Abstract: A method for fabricating semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer, forming two via holes and a trench in the first IMD layer, forming a metal layer in the two via holes and the trench for forming a metal interconnection and a spin orbit torque (SOT) layer, forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first hard mask on the MTJ, forming a second hard mask on the first hard mask, forming a cap layer adjacent to the MTJ, and forming a second IMD layer around the cap layer.
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公开(公告)号：US20230154514A1
公开(公告)日：2023-05-18
申请号：US17548583
申请日：2021-12-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Yu-Ping Wang , Chien-Ting Lin
CPC classification number: G11C11/161 , H01L43/12 , H01L43/10 , H01L43/08 , H01L43/02 , H01L27/222
Abstract: The invention provides a semiconductor structure, which comprises an MTJ (magnetic tunneling junction) stacked structure arranged on a substrate, and a SOT (spin orbit torque) layer arranged on the MTJ stacked structure, wherein the SOT layer comprises a first part with a thick thickness and two second parts with a thin thickness.
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公开(公告)号：US11309486B2
公开(公告)日：2022-04-19
申请号：US16719992
申请日：2019-12-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Yu-Ping Wang , Hung-Yueh Chen
Abstract: A magnetoresistive random access memory (MRAM) is provided in the present invention, including a conductive plug with a protruding portion extending outwardly on one side and a notched portion concaving inwardly on the other side of the upper edge of conductive plug, and a memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction (MTJ) on the bottom electrode, and a top electrode on the magnetic tunnel junction, wherein the bottom surface of memory cell completely overlaps the top surface of conductive plug.
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公开(公告)号：US11050017B2
公开(公告)日：2021-06-29
申请号：US16850003
申请日：2020-04-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yu-Chun Chen , Ya-Sheng Feng , Chiu-Jung Chiu , Hung-Chan Lin
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the MTJ, and a second spacer on another side of the MTJ, in which the first spacer and the second spacer are asymmetric. Specifically, the MTJ further includes a first bottom electrode disposed on a metal interconnection, a capping layer on the bottom electrode, and a top electrode on the capping layer, in which a top surface of the first spacer is even with a top surface of the top electrode and a top surface of the second spacer is lower than the top surface of the top electrode and higher than the top surface of the capping layer.
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公开(公告)号：US20210036053A1
公开(公告)日：2021-02-04
申请号：US17074643
申请日：2020-10-20
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chia-Chang Hsu , Chen-Yi Weng , Hung-Chan Lin , Jing-Yin Jhang , Yu-Ping Wang
IPC: H01L27/22 , G11C11/16 , H01L23/48 , H01L43/12 , H01L23/544 , H01L21/321 , H01L21/762 , H01L23/485
Abstract: The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer.
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Patent Agency Ranking
公开(公告)号：US10529920B1
公开(公告)日：2020-01-07
申请号：US16056551
申请日：2018-08-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ya-Sheng Feng , Hung-Chan Lin , Yu-Ping Wang , Yu-Chun Chen , Chiu-Jung Chiu
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a magnetic tunneling junction (MTJ) on the first IMD layer; forming a liner on the MTJ and the first IMD layer; removing part of the liner to form a spacer adjacent to the MTJ; and forming a second IMD layer on the first IMD layer.
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公开(公告)号：US09947673B1
公开(公告)日：2018-04-17
申请号：US15479253
申请日：2017-04-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ting-Chia Chang , Shih-Hao Liang , Chun-Yen Tseng , Yu-Tse Kuo , Ching-Cheng Lung , Hung-Chan Lin , Shao-Hui Wu
IPC: H01L27/02 , H01L27/11 , G11C11/412 , H01L29/24
CPC classification number: H01L27/1104 , G11C11/412 , G11C14/0054 , H01L27/0207 , H01L27/1116 , H01L29/24
Abstract: The present invention provides a semiconductor memory device, includes at least one static random access memory (SRAM) cell, wherein the SRAM cell includes a first pick-up node, and a dielectric oxide SRAM (DOSRAM), disposed in a first dielectric layer and disposed above the SRAM cell when viewed in a cross section view, wherein the DOSRAM includes an oxide semiconductor filed effect transistor (OSFET) and a capacitor, a source of the OSFET is electrically connected to the first pick-up node of the SRAM cell through a via structure, and at least parts of the first dielectric layer are disposed between the source of the OSFET and the via structure, and the capacitor is disposed above the OSFET and electrically connected to a drain of the OSFET when viewed in the cross section view.
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公开(公告)号：US20250054880A1
公开(公告)日：2025-02-13
申请号：US18369207
申请日：2023-09-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Chang-Yih Chen
IPC: H01L23/00 , H01L21/768 , H10B61/00
Abstract: A method for fabricating a physically unclonable function (PUF) device includes the steps of firs providing a substrate comprising a magnetoresistive random access memory (MRAM) region, a PUF cell region, and a non-PUF cell region, forming a first metal interconnection on the MRAM region, forming a second metal interconnection on the PUF cell region, and forming a third metal interconnection on the non-PUF cell region. Preferably, the first metal interconnection and the second metal interconnection include patterns of different shapes and the first metal interconnection and the third metal interconnection include patterns of same shape.
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公开(公告)号：US20240237554A1
公开(公告)日：2024-07-11
申请号：US18611729
申请日：2024-03-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Yu-Ping Wang , Chien-Ting Lin
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a spacer adjacent to the MTJ and the first SOT layer, and a second SOT layer on the first SOT layer. Preferably, the first SOT layer and the second SOT layer are made of same material.
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公开(公告)号：US20240237553A1
公开(公告)日：2024-07-11
申请号：US18611723
申请日：2024-03-21
Applicant: United Microelectronics Corp.
Inventor： Hung-Chan Lin , Yu-Ping Wang , Chien-Ting Lin
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a second SOT layer on the first SOT layer, a hard mask between the first SOT layer and the second SOT layer, and a spacer adjacent to the MTJ, the first SOT layer, and the hard mask.
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