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1.发明授权Programmable logic device having a plurality of programmable logic arrays arranged in a mosaic layout together with a plurality of interminglingly arranged interfacing blocks 失效具有多个可编程逻辑阵列的可编程逻辑器件与多个混合布置的接口块一起以马赛克布局布置
公开(公告)号：US4992680A
公开(公告)日：1991-02-12
申请号：US456782
申请日：1989-12-27
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177 , H03K23/54
CPC分类号： H03K19/1735 , H03K19/17708 , H03K23/542
摘要： A programmable logic device has an architecture which permits to implement logic functions through loopable multi-levels by utilizing a network of distributed memory arrays organized as a mosaic of arrays of programmable memory cells and multifunctional interfacing blocks. Each of said blocks contains an input selection circuitry capable of receiving input signals coming from bidirectional input/output pins and/or from outputs of said arrays, signal selection means, polarity selection means and path selection means and an output sorting circuitry capable of selecting non-stored or stored type, data containing signals, selecting the polarity and the path of said signals toward enableable output drive buffers of said plurality of bidirectional input/output pins and/or toward the inputs of any one of said arrays, a circuitry capable of producing for each of said signals a first, non-inverted, and a second, inverted, buffered replica signals with which to drive the rows of one or more of said memory arrays for causing the output of signals from those arrays, each array being programmable in order to perform different logic functions for any combination of inputs thereof and the exchange between two different arrays and between an array and the external world taking place essentially through at least one of said multfunctional blocks.
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公开(公告)号：US4839768A
公开(公告)日：1989-06-13
申请号：US113113
申请日：1987-10-27
IPC分类号： H05F3/02 , H01L21/331 , H01L21/822 , H01L21/8234 , H01L27/02 , H01L27/04 , H01L27/06 , H01L27/088 , H01L29/73 , H01L29/78
CPC分类号： H01L27/0255 , H01L27/0251 , Y10S257/927
摘要： The influence of the resistance of the connection between a terminal of voltage limiting diodes against discharges of electrostatic nature which may hit a pad of an integrated circuit and a respective common potential node of the integrated circuit (supply or ground node) is unsuspectably critical. A resistance of just few ohms may depress the maximum tolerable discharge voltage by several thousands volts and the relationship between such two parameters is hyperbolic. Such a critical resistance may advantageously be reduced by utilizing more levels of metallization purposely connected in parallel and/or by "shifting" the protection diodes near the real (and not virtual) common potential node of the circuit or by utilizing "ring" metallizations over different levels for both the common potential nodes of the circuit.
摘要翻译： 电压限制二极管的端子与可能撞击集成电路的焊盘和集成电路（电源或接地节点）的相应公共电位节点的静电特性的连接的电阻的影响是无关紧要的。 只有几欧姆的电阻可能会使最大容许放电电压下降几千伏特，并且这两个参数之间的关系是双曲线的。 这种临界电阻可以有利地通过利用更多级别的金属化来有目的地并联连接和/或通过在电路的实际（而不是虚拟的）公共电位节点附近的“移位”保护二极管，或者通过利用“环”金属化 电路的共同电位节点的不同电平。
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公开(公告)号：US5412599A
公开(公告)日：1995-05-02
申请号：US951274
申请日：1992-09-25
IPC分类号： H03K17/00 , H03K17/62 , H03K17/687 , H03K17/693 , G11C7/02 , H03K19/096
CPC分类号： H03K17/6235 , H03K17/6872 , H03K17/693 , H03K2217/0036
摘要： A null consumption CMOS switch which may be set by nonvolatile programming is formed by a pair of complementary transistors preferably having a common drain and a common gate. The common gate is coupled to the floating gate a programmable and erasable, nonvolatile memory cell. The common gate/floating gate coupling can be a unitary floating gate structure. The floating gate directly drives the ON or OFF states of the two complementary transistors. On an output node of the switch, represented by the common drain of the pair of transistors, a signal present on a source node of one or the other of the two complementary transistors is replicated. The state of charge of the floating gate, imposed by programming or erasing, may be such as to reach advantageously a potential higher than the supply voltage or lower than the ground potential of the circuit. Different embodiments, such as a polarity selection, a path selector, a TRISTATE selector, and a logic gate selector are described.
摘要翻译： 可以由非易失性编程设置的零消耗CMOS开关由优选具有公共漏极和公共栅极的一对互补晶体管形成。 公共栅极耦合到浮动栅极可编程和可擦除的非易失性存储单元。 公共栅极/浮动栅极耦合可以是单一的浮动栅极结构。 浮栅直接驱动两个互补晶体管的导通或截止状态。 在由一对晶体管的公共漏极表示的开关的输出节点上，复制存在于两个互补晶体管中的一个或另一个的源极节点上的信号。 通过编程或擦除施加的浮动栅极的充电状态可以有利地达到高于电源电压或低于电路的地电位的电位。 描述了诸如极性选择，路径选择器，TRISTATE选择器和逻辑门选择器的不同实施例。
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4.发明授权TTL compatible CMOS logic circuit for driving heavy capacitive loads at high speed 失效TTL兼容CMOS逻辑电路，用于高速驱动大容量负载
公开(公告)号：US4868422A
公开(公告)日：1989-09-19
申请号：US130815
申请日：1987-12-09
IPC分类号： H01L21/8238 , H01L27/092 , H03K19/00 , H03K19/017 , H03K19/0948
CPC分类号： H03K19/0948 , H03K19/0005 , H03K19/01707
摘要： CMOS logic circuit with one or more inputs has at least a complementary pair of transistors, the N-channel driver transistor having a gate directly connected to an input while the P-channel load transistor having a gate connected to the output of the second one of two inverters connected in cascade, the input of the first inverter being connected to the input of the circuit. Using two signal inverting stages or inverters for mirroring the input signal on the gate of the load P-channel transistor of the circuit pair permits the defining of the triggering threshold of the circuit with great freedom, the obtaining of a greater switching speed and the reduction of power dissipation under stand-by conditions. The invention is particularly suited for HCT circuits.
摘要翻译： 具有一个或多个输入的CMOS逻辑电路具有至少一对互补晶体管，所述N沟道驱动晶体管具有与输入端直接连接的栅极，而P沟道负载晶体管具有与第二个晶体管的输出端连接的栅极 两个串联连接的逆变器，第一反相器的输入端连接到电路的输入端。 使用两个信号反相级或反相器来反映电路对的负载P沟道晶体管的栅极上的输入信号，可以大大自由地定义电路的触发阈值，获得更大的开关速度和降低 在待机条件下的功耗。 本发明特别适用于HCT电路。
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5.发明授权Monolithically integrated programmable device having elementary modules connected electrically by means of memory cells of the flash type 失效具有通过闪存类型的存储器单元电连接的基本模块的单片式可编程器件
公开(公告)号：US6005411A
公开(公告)日：1999-12-21
申请号：US777296
申请日：1996-12-27
申请人： Vincenzo Daniele
发明人： Vincenzo Daniele
IPC分类号： H03K19/173 , H03K19/177 , H03K19/094
CPC分类号： H03K19/17708 , H03K19/1736
摘要： The present invention is a monolithically integrated programmable device having elementary modules connected electrically by means of memory cells of the flash type, which cells allow the signal paths between signal lines of the elementary modules to be programmed and re-programmed. Preferably, the flash memory cells are Fowler-Nordheim Effect cells.
摘要翻译： 本发明是具有通过闪存类型的存储器单元电连接的基本模块的单片集成可编程器件，这些单元允许对基本模块的信号线之间的信号路径进行编程和重新编程。 优选地，闪存单元是Fowler-Nordheim Effect细胞。
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公开(公告)号：US5949666A
公开(公告)日：1999-09-07
申请号：US32282
申请日：1998-02-26
摘要： A staircase adaptive voltage generator circuit comprising a first capacitor connected between a first voltage reference and an output operational amplifier, through first and second switches, respectively. The terminals of the capacitor are also connected to a second voltage reference through third and fourth switches, respectively. A second capacitor, in series with a fifth switch, is connected in parallel to the first capacitor.
摘要翻译： 一种楼梯自适应电压发生器电路，包括分别通过第一和第二开关连接在第一电压基准和输出运算放大器之间的第一电容器。 电容器的端子也分别通过第三和第四开关连接到第二参考电压。 与第五开关串联的第二电容器与第一电容器并联连接。
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7.发明授权Analog integrated circuit having intrinsic topologies and characteristics selectable by a digital control 失效具有可由数字控制选择的固有拓扑和特性的模拟集成电路
公开(公告)号：US4875020A
公开(公告)日：1989-10-17
申请号：US287299
申请日：1988-12-21
CPC分类号： G06J1/00
摘要： An integrated analog circuit having a circuit topology and intrinsic characteristics which may be selected by digital control means is formed by batteries of similar circuit components arranged substantially in parallel or in a matrix array, anyone of which may be isolated or not by means of a dedicated integrated switch and by alternative interconnection paths among the different circuit components and/or batteries of circuit components, which may be also be selected by closing a relative integrated switch. A dedicated nonvolatile memory, integrated on the same chip may be permanently programmed and determine a certain configuration of all the integrated switches thus selected a particlar component or more components of each of said batteries of functionally similar components, and/or selecting a certain interconnection path among the different circuit components in order to form a functional integrated circuit having the desired topology and intrinsic characteristics. The integrated nonvolatile memory is programmed by means of a software program which may take as input data the desired values of the different parameters which determine the intrinsic characteristics of the functional analog circuit and the type of functional analog circuit itself.
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8.发明授权Circuit and method for reading a memory cell that can store multiple bits of data 失效用于读取可存储多个数据位的存储单元的电路和方法
公开(公告)号：US5673221A
公开(公告)日：1997-09-30
申请号：US592939
申请日：1996-01-29
申请人： Cristiano Calligaro , Vincenzo Daniele , Roberto Gastaldi , Alessandro Manstretta , Nicola Telecco , Guido Torelli
发明人： Cristiano Calligaro , Vincenzo Daniele , Roberto Gastaldi , Alessandro Manstretta , Nicola Telecco , Guido Torelli
CPC分类号： G11C11/5621 , G11C11/5642 , G11C2211/5632
摘要： A sensing circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2.sup.n (n>=2) different programming levels, comprises biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of the programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator. The variable reference current generator comprises an offset current generator permanently coupled to the current comparator, and m-2 distinct current generators, independently activatable by the successive approximation register, each one generating a current equal to a respective one of the plurality of cell current values.
摘要翻译： 用于在多个m = 2n（n> = 2）不同编程级别中可以采用一个编程级的多级存储器单元的串行二分感测的感测电路包括偏置装置，用于以预定的方式偏置待感测的存储器单元 条件，使得存储器单元以属于多个m个不同的单元电流值的值吸收单元电流，每个单元电流值对应于一个编程电平，用于将单元电流与产生的参考电流进行比较的电流比较器 通过可变参考电流发生器和逐次逼近寄存器来提供电流比较器的输出信号并控制可变参考电流发生器。 可变参考电流发生器包括永久地耦合到电流比较器的偏移电流发生器和由逐次逼近寄存器独立激活的m-2个不同的电流发生器，每个电流发生器产生等于多个电池电流值中的相应一个的电流 。
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公开(公告)号：US4310571A
公开(公告)日：1982-01-12
申请号：US34204
申请日：1979-04-27
IPC分类号： H01C17/24 , H01L21/02 , H01L21/033 , H01L21/82 , H01L21/822 , H01L27/04 , H01L27/10 , H01C17/06
CPC分类号： H01L28/20 , H01L21/033 , Y10T29/49082 , Y10T29/49099
摘要： Filiform elements of predetermined resistivity, e.g. selectively destructible leads of an electrically programmable read-only memory, are formed on a semiconductor substrate such as a silicon body by first depositing thereon a layer of dielectric material such as SiO.sub.2 and topping that layer with a conductive or nonconductive coating which is resistant to a chemical such as hydrofluoric acid capable of attacking the dielectric layer. Next, the top coating is partly destroyed by photolithographic treatment to leave at least one substantially rectangular patch. Thereafter, the dielectric layer is isotropically attacked by the aforementioned chemical with resulting reduction to about half its original thickness and concurrent lateral erosion of a patch-supporting pedestal of that layer whereby channels of generally semicylindrical concavity are formed around the periphery of this pedestal. The patch, if composed of conductive or semiconductive material, is then clad in an insulating envelope whereupon the dielectric layer and the patch are covered with a deposit of the desired electrical conductivity which could consist of doped polycrystalline silicon or of metal. Finally, this deposit is removed by chemical or ionic etching except in the channels of the pedestal and along a pair of parallel strips adjoining opposite pedestal sides whereby these strips remain electrically interconnected by filiform inserts left in the undercuts of the other two sides.
摘要翻译： 预定电阻率的丝状元素，例如 通过首先在诸如硅体的半导体衬底上沉积介电材料层（例如SiO 2）形成电可编程只读存储器的选择性可破坏的引线，并用导电或非导电涂层将该层顶起来，该导电或非导电涂层对 化学物质如能够侵蚀电介质层的氢氟酸。 接下来，通过光刻处理部分地破坏顶部涂层以留下至少一个基本上矩形的贴片。 此后，电介质层被上述化学物质各向同性地侵蚀，从而将其降低到其原始厚度的大约一半，并且该层的贴片支撑基座的同时横向侵蚀，从而在该基座的周边周围形成大致半圆柱形凹陷的通道。 如果由导电材料或半导体材料组成，则贴片被覆在绝缘包层中，由介电层和贴片用可掺杂多晶硅或金属的所需电导率的沉积物覆盖。 最后，通过化学或离子蚀刻除去基座的通道以及邻接相对的基座侧的一对平行条，除去这些沉积物，由此这些条通过留在另外两边的底切部中的丝状插入物而保持电互连。
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10.再颁专利Circuit and method for reading a memory cell that can store multiple bits of data 有权用于读取可存储多个数据位的存储单元的电路和方法公开(公告)号：USRE38166E1
公开(公告)日：2003-07-01
申请号：US09410164
申请日：1999-09-30
申请人： Cristiano Calligaro , Vincenzo Daniele , Roberto Gastaldi , Alessandro Manstretta , Nicola Telecco , Guido Torelli
发明人： Cristiano Calligaro , Vincenzo Daniele , Roberto Gastaldi , Alessandro Manstretta , Nicola Telecco , Guido Torelli
IPC分类号： G11C1156
CPC分类号： G11C11/5621 , G11C11/5642 , G11C2211/5632
摘要： A sensing circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2n (n>=2) different programming levels, comprises biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of the programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator. The variable reference current generator comprises an offset current generator permanently coupled to the current comparator, and m−2 distinct current generators, independently activatable by the successive approximation register, each one generating a current equal to a respective one of the plurality of cell current values.
摘要翻译： 用于在多个m = 2n（n> = 2）不同编程级别中可以采用一个编程级的多级存储器单元的串行二分感测的感测电路包括偏置装置，用于以预定的方式偏置待感测的存储器单元 条件，使得存储器单元以属于多个m个不同的单元电流值的值吸收单元电流，每个单元电流值对应于一个编程电平，用于将单元电流与产生的参考电流进行比较的电流比较器 通过可变参考电流发生器和逐次逼近寄存器来提供电流比较器的输出信号并控制可变参考电流发生器。 可变参考电流发生器包括永久地耦合到电流比较器的偏移电流发生器和由逐次逼近寄存器独立激活的m-2个不同的电流发生器，每个电流发生器产生等于多个电池电流值中的相应一个的电流 。
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