摘要:
A memory manufactured through a semiconductor process includes a substrate, a memory cell array formed on the substrate, a peripheral circuit formed on the substrate and electrically connected to the memory cell array for controlling access of the memory cell array, and a power distribution network formed substantially above the peripheral circuit or the memory cell array. The power distribution network is electrically connected to the peripheral circuit and the memory cell array for providing power to the peripheral circuit and the memory cell array.
摘要:
The invention provides a memory output circuit. The memory output circuit is capable of receiving bit line data and bit bar line data output by a memory cell array. In one embodiment, the memory output circuit comprises a pre-charge circuit, a pre-amplifier circuit, and a sense amplifier. The pre-charge circuit is capable of pre-charging a first node and a first inverse node wherein the bit line data and bit bar line data are respectively output to the first node and the first inverse node. The pre-amplifier circuit is capable of generating a second voltage on a second node and a second inverse voltage on a second inverse node according to a first voltage on the first node and a first inverse voltage on the first inverse node. The sense amplifier is capable of detecting the second voltage on the second node and the second inverse voltage on the second inverse node to generate a third voltage on a third node and a third inverse voltage on a third inverse node.
摘要:
A method for performing a delay lock to generate a second clock according to a first clock and to synchronize the second clock with the first clock is provided. The method has correcting processes executed to increase or decrease, by a correction interval, a delay time between corresponding periods of the first clock and the second clock. The correction interval for a subsequent correcting process is substantially half the previous correction interval of the previous correcting process.
摘要:
A method is proposed for eliminating signal skew in an SDRAM (Synchronized Dynamic Random-Access Memory) device resulting from the data signal being attenuated into different input signal amplitudes at the respective input points into the memory cells in the SDRAM device. The method is intended for use on a SDRAM device having at least a first memory cell and a second memory cell which are connected to a common signal line which transmits a data signal to both the first and the second memory cells. Due to the data signal being gradually attenuated along the signal line, the input signal amplitudes at the respective input points into the first and second memory cells are different, which would otherwise cause signal skew. In accordance with this method, the trigger voltage levels of the memory cells are adjusted in such a manner as to be substantially equal to the respective input signal amplitudes at a specific trigger time, so that all the memory cells can be triggered substantially concurrently without the occurrence of signal skew. Typically, the trigger voltage levels can be adjusted by adjusting the respective threshold voltages or current gains of the NMOS transistor and PMOS transistor in an inverter used as the I/O buffer of each memory cell. By this method, the adjustment can be easily achieved without having to provide additional circuitry to the SDRAM device. This method is therefore useful in solving the problem of signal skew in the SDRAM device.
摘要:
The invention provides a memory circuit. In one embodiment, the memory circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a memory cell array. The first PMOS transistor is coupled between a first voltage terminal and a first node. The second PMOS transistor is coupled between the first voltage terminal and a second node. The first NMOS transistor is coupled between a third node and a second voltage terminal. The second NMOS transistor is coupled between a fourth node and the second voltage terminal. The memory cell array comprises a plurality of memory cells, at least one comprising a first inverter and a second inverter. A positive power terminal of the first inverter is coupled to the first node, a negative power terminal of the first inverter is coupled to the third node, a positive power terminal of the second inverter is coupled to the second node, and a negative power terminal of the second inverter is coupled to the fourth node.
摘要:
A sensing circuit for sensing logic data is shown. A memory cell is electrically connected to a bit line. The sensing circuit includes a first pre-charging module electrically connected to the bit line for pre-charging the bit line. A selecting module is electrically connected between the bit line and a first data line for transmitting signals and for isolating capacitances. A second pre-charging module is electrically connected to the first data line for pre-charging the first data line. A first voltage keeping module is electrically connected to the first data line for maintaining a signal on the first data line at a voltage level. An isolating module is electrically connected between the first data line and a second data line for transmitting signals and for isolating capacitances. A third pre-charging module is electrically connected to the second data line for pre-charging the second data line.
摘要:
A sensing circuit for sensing logic data is disclosed. A memory cell is electrically connected to a bit line. The sensing circuit includes a first pre-charging module electrically connected to the bit line for pre-charging the bit line. A selecting module is electrically connected between the bit line and a first data line for transmitting signals and for isolating capacitances. A second pre-charging module is electrically connected to the first data line for pre-charging the first data line. A first voltage keeping module is electrically connected to the first data line for maintaining a signal on the first data line at a voltage level. An isolating module is electrically connected between the first data line and a second data line for transmitting signals and for isolating capacitances. A third pre-charging module is electrically connected to the second data line for pre-charging the second data line.
摘要:
A sense/output circuit is designed for use with a memory device, such as an SDRAM (Synchronized Dynamic Random-Access Memory) device, which is capable of switching off some power-consuming circuit components immediately after the requested data output is completed. This feature can help reduce the power consumption by the overall memory system, making the use of the SDRAM device more cost-effective. Moreover, the reduction of power consumption can be achieved without concerning process parameters, component parameters, and temperature variations. As a result, the delay margin can be reduced compared to the prior art, which also contribute to the reduction of power consumption.
摘要:
The invention provides a memory output circuit. The memory output circuit is capable of receiving bit line data and bit bar line data output by a memory cell array. In one embodiment, the memory output circuit comprises a pre-charge circuit, a pre-amplifier circuit, and a sense amplifier. The pre-charge circuit is capable of pre-charging a first node and a first inverse node wherein the bit line data and bit bar line data are respectively output to the first node and the first inverse node. The pre-amplifier circuit is capable of generating a second voltage on a second node and a second inverse voltage on a second inverse node according to a first voltage on the first node and a first inverse voltage on the first inverse node. The sense amplifier is capable of detecting the second voltage on the second node and the second inverse voltage on the second inverse node to generate a third voltage on a third node and a third inverse voltage on a third inverse node.
摘要:
A pre-charge and sense out circuit for differential type ROM. The ROM is capable of connecting to either a first bit line or a second bit line. The pre-charge and sense out circuit contains a pre-charging module electrically connected to the first and the second bit lines, for pre-charging the first and the second bit lines; a selecting module electrically connected to the first bit line, the second bit line, a first data line, and a second data line, for transmitting data according to a first control signal; a charge sharing module electrically connected to the first and the second data lines, for sharing electrical charges to the first and the second data lines; and a sensing module electrically connected to the first and the second data lines, for sensing signals on the first and the second data lines so as to generate an output signal.