公开(公告)号：US20060104101A1

公开(公告)日：2006-05-18

申请号：US10904573

申请日：2004-11-17

申请人： Wen-Lin Chen ,  Yung-Chieh Yu ,  Po-Sen Wang ,  Shih-Huang Huang

发明人： Wen-Lin Chen ,  Yung-Chieh Yu ,  Po-Sen Wang ,  Shih-Huang Huang

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C5/025 ,  G11C5/14

摘要： A memory manufactured through a semiconductor process includes a substrate, a memory cell array formed on the substrate, a peripheral circuit formed on the substrate and electrically connected to the memory cell array for controlling access of the memory cell array, and a power distribution network formed substantially above the peripheral circuit or the memory cell array. The power distribution network is electrically connected to the peripheral circuit and the memory cell array for providing power to the peripheral circuit and the memory cell array.

摘要翻译： 通过半导体工艺制造的存储器包括基板，形成在基板上的存储单元阵列，形成在基板上并与存储单元阵列电连接以控制存储单元阵列的存取的外围电路，以及形成的配电网 大致高于外围电路或存储单元阵列。 配电网络电连接到外围电路和存储单元阵列，以向外围电路和存储单元阵列供电。

公开(公告)号：US08837244B2

公开(公告)日：2014-09-16

申请号：US13176858

申请日：2011-07-06

申请人： Shih-Huang Huang

发明人： Shih-Huang Huang

IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C7/18 ,  G11C7/06 ,  G11C7/12

CPC分类号： G11C7/062 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/12 ,  G11C7/18

摘要： The invention provides a memory output circuit. The memory output circuit is capable of receiving bit line data and bit bar line data output by a memory cell array. In one embodiment, the memory output circuit comprises a pre-charge circuit, a pre-amplifier circuit, and a sense amplifier. The pre-charge circuit is capable of pre-charging a first node and a first inverse node wherein the bit line data and bit bar line data are respectively output to the first node and the first inverse node. The pre-amplifier circuit is capable of generating a second voltage on a second node and a second inverse voltage on a second inverse node according to a first voltage on the first node and a first inverse voltage on the first inverse node. The sense amplifier is capable of detecting the second voltage on the second node and the second inverse voltage on the second inverse node to generate a third voltage on a third node and a third inverse voltage on a third inverse node.

摘要翻译： 本发明提供一种存储器输出电路。 存储器输出电路能够接收由存储单元阵列输出的位线数据和位线数据。 在一个实施例中，存储器输出电路包括预充电电路，前置放大器电路和读出放大器。 预充电电路能够对第一节点和第一逆节点进行预充电，其中位线数据和位线数据被分别输出到第一节点和第一逆节点。 前置放大器电路能够根据第一节点上的第一电压和第一反向节点上的第一反向电压在第二节点上产生第二电压和第二反向节点上的第二反向电压。 感测放大器能够检测第二节点上的第二电压和第二反向节点上的第二反向电压，以在第三节点上产生第三电压，并在第三反向节点上产生第三反向电压。

公开(公告)号：US06900678B2

公开(公告)日：2005-05-31

申请号：US09682303

申请日：2001-08-16

申请人： Jui-Lung Chen ,  Shih-Huang Huang

发明人： Jui-Lung Chen ,  Shih-Huang Huang

IPC分类号： H03L7/081 ,  H03L7/10 ,  H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/10

摘要： A method for performing a delay lock to generate a second clock according to a first clock and to synchronize the second clock with the first clock is provided. The method has correcting processes executed to increase or decrease, by a correction interval, a delay time between corresponding periods of the first clock and the second clock. The correction interval for a subsequent correcting process is substantially half the previous correction interval of the previous correcting process.

摘要翻译： 提供一种用于执行延迟锁以根据第一时钟产生第二时钟并使第二时钟与第一时钟同步的方法。 该方法具有执行校正处理，以通过校正间隔增加或减少第一时钟和第二时钟的相应周期之间的延迟时间。 用于后续校正处理的校正间隔实际上是先前校正处理的先前校正间隔的一半。

公开(公告)号：US6118731A

公开(公告)日：2000-09-12

申请号：US389817

申请日：1999-09-03

申请人： Shih-Huang Huang ,  Hsin-Pang Lu

发明人： Shih-Huang Huang ,  Hsin-Pang Lu

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1072 ,  G11C7/1051 ,  G11C7/1078

摘要： A method is proposed for eliminating signal skew in an SDRAM (Synchronized Dynamic Random-Access Memory) device resulting from the data signal being attenuated into different input signal amplitudes at the respective input points into the memory cells in the SDRAM device. The method is intended for use on a SDRAM device having at least a first memory cell and a second memory cell which are connected to a common signal line which transmits a data signal to both the first and the second memory cells. Due to the data signal being gradually attenuated along the signal line, the input signal amplitudes at the respective input points into the first and second memory cells are different, which would otherwise cause signal skew. In accordance with this method, the trigger voltage levels of the memory cells are adjusted in such a manner as to be substantially equal to the respective input signal amplitudes at a specific trigger time, so that all the memory cells can be triggered substantially concurrently without the occurrence of signal skew. Typically, the trigger voltage levels can be adjusted by adjusting the respective threshold voltages or current gains of the NMOS transistor and PMOS transistor in an inverter used as the I/O buffer of each memory cell. By this method, the adjustment can be easily achieved without having to provide additional circuitry to the SDRAM device. This method is therefore useful in solving the problem of signal skew in the SDRAM device.

摘要翻译： 提出了一种用于消除SDRAM（同步动态随机存取存储器）中的信号偏移的方法，该信号由数据信号衰减到各个输入点处的不同输入信号幅度，进入SDRAM器件中的存储单元。 该方法旨在用于具有至少第一存储器单元和第二存储器单元的SDRAM器件，该第一存储器单元和第二存储器单元连接到向第一和第二存储器单元发送数据信号的公共信号线。 由于数据信号沿着信号线逐渐衰减，所以进入第一和第二存储器单元的各个输入点的输入信号幅度不同，否则会导致信号偏移。 按照这种方法，存储器单元的触发电压电平被调节成基本上等于在特定触发时间的相应输入信号幅度，使得所有的存储单元可以基本同时触发，而没有 出现信号偏移。 通常，可以通过调整用作每个存储单元的I / O缓冲器的反相器中的NMOS晶体管和PMOS晶体管的相应阈值电压或电流增益来调整触发电压电平。 通过这种方法，可以容易地实现调整，而不必向SDRAM设备提供额外的电路。 因此，该方法可用于解决SDRAM器件中的信号偏移问题。

公开(公告)号：US20130010531A1

公开(公告)日：2013-01-10

申请号：US13176852

申请日：2011-07-06

申请人： Shih-Huang Huang

发明人： Shih-Huang Huang

IPC分类号： G11C11/00 ,  G11C5/14

CPC分类号： G11C7/12 ,  G11C5/148 ,  G11C7/20 ,  G11C8/08 ,  G11C11/418 ,  G11C2207/2227

摘要： The invention provides a memory circuit. In one embodiment, the memory circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a memory cell array. The first PMOS transistor is coupled between a first voltage terminal and a first node. The second PMOS transistor is coupled between the first voltage terminal and a second node. The first NMOS transistor is coupled between a third node and a second voltage terminal. The second NMOS transistor is coupled between a fourth node and the second voltage terminal. The memory cell array comprises a plurality of memory cells, at least one comprising a first inverter and a second inverter. A positive power terminal of the first inverter is coupled to the first node, a negative power terminal of the first inverter is coupled to the third node, a positive power terminal of the second inverter is coupled to the second node, and a negative power terminal of the second inverter is coupled to the fourth node.

摘要翻译： 本发明提供一种存储器电路。 在一个实施例中，存储器电路包括第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二PMOS晶体管和存储单元阵列。 第一PMOS晶体管耦合在第一电压端子和第一节点之间。 第二PMOS晶体管耦合在第一电压端子和第二节点之间。 第一NMOS晶体管耦合在第三节点和第二电压端子之间。 第二NMOS晶体管耦合在第四节点和第二电压端子之间。 存储单元阵列包括多个存储单元，至少一个存储单元包括第一反相器和第二反相器。 第一反相器的正电源端子耦合到第一节点，第一反相器的负电源端子耦合到第三节点，第二反相器的正电源端子耦合到第二节点，负电源端子 的第二反相器耦合到第四节点。

公开(公告)号：US07130233B2

公开(公告)日：2006-10-31

申请号：US10906069

申请日：2005-02-01

申请人： Shih-Huang Huang

发明人： Shih-Huang Huang

IPC分类号： G11C7/00

CPC分类号： G11C17/12 ,  G11C7/065 ,  G11C7/067

摘要： A sensing circuit for sensing logic data is shown. A memory cell is electrically connected to a bit line. The sensing circuit includes a first pre-charging module electrically connected to the bit line for pre-charging the bit line. A selecting module is electrically connected between the bit line and a first data line for transmitting signals and for isolating capacitances. A second pre-charging module is electrically connected to the first data line for pre-charging the first data line. A first voltage keeping module is electrically connected to the first data line for maintaining a signal on the first data line at a voltage level. An isolating module is electrically connected between the first data line and a second data line for transmitting signals and for isolating capacitances. A third pre-charging module is electrically connected to the second data line for pre-charging the second data line.

摘要翻译： 示出了用于感测逻辑数据的感测电路。 存储单元电连接到位线。 感测电路包括电连接到位线以预充电位线的第一预充电模块。 选择模块电连接在位线和用于传输信号和隔离电容的第一数据线之间。 第二预充电模块电连接到第一数据线，用于对第一数据线进行预充电。 第一电压保持模块电连接到第一数据线，用于将第一数据线上的信号保持在电压电平。 隔离模块电连接在第一数据线和第二数据线之间，用于传输信号和隔离电容。 第三预充电模块电连接到第二数据线，用于对第二数据线进行预充电。

公开(公告)号：US20050105340A1

公开(公告)日：2005-05-19

申请号：US10906069

申请日：2005-02-01

申请人： Shih-Huang Huang

发明人： Shih-Huang Huang

IPC分类号： G11C7/06 ,  G11C16/06 ,  G11C17/12

CPC分类号： G11C17/12 ,  G11C7/065 ,  G11C7/067

摘要： A sensing circuit for sensing logic data is disclosed. A memory cell is electrically connected to a bit line. The sensing circuit includes a first pre-charging module electrically connected to the bit line for pre-charging the bit line. A selecting module is electrically connected between the bit line and a first data line for transmitting signals and for isolating capacitances. A second pre-charging module is electrically connected to the first data line for pre-charging the first data line. A first voltage keeping module is electrically connected to the first data line for maintaining a signal on the first data line at a voltage level. An isolating module is electrically connected between the first data line and a second data line for transmitting signals and for isolating capacitances. A third pre-charging module is electrically connected to the second data line for pre-charging the second data line.

摘要翻译： 公开了一种用于感测逻辑数据的感测电路。 存储单元电连接到位线。 感测电路包括电连接到位线以预充电位线的第一预充电模块。 选择模块电连接在位线和用于传输信号和隔离电容的第一数据线之间。 第二预充电模块电连接到第一数据线，用于对第一数据线进行预充电。 第一电压保持模块电连接到第一数据线，用于将第一数据线上的信号保持在电压电平。 隔离模块电连接在第一数据线和第二数据线之间，用于传输信号和隔离电容。 第三预充电模块电连接到第二数据线，用于对第二数据线进行预充电。

公开(公告)号：US6058059A

公开(公告)日：2000-05-02

申请号：US385737

申请日：1999-08-30

申请人： Shih-Huang Huang ,  Hsin-Pang Lu

发明人： Shih-Huang Huang ,  Hsin-Pang Lu

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/02

CPC分类号： G11C7/062 ,  G11C7/1051

摘要： A sense/output circuit is designed for use with a memory device, such as an SDRAM (Synchronized Dynamic Random-Access Memory) device, which is capable of switching off some power-consuming circuit components immediately after the requested data output is completed. This feature can help reduce the power consumption by the overall memory system, making the use of the SDRAM device more cost-effective. Moreover, the reduction of power consumption can be achieved without concerning process parameters, component parameters, and temperature variations. As a result, the delay margin can be reduced compared to the prior art, which also contribute to the reduction of power consumption.

摘要翻译： 感测/输出电路设计用于诸如SDRAM（同步动态随机存取存储器）之类的存储器件，其能够在所请求的数据输出完成之后立即关闭一些耗电的电路部件。 该功能可以帮助降低整个存储系统的功耗，使SDRAM设备的使用更具成本效益。 此外，可以在不涉及工艺参数，部件参数和温度变化的情况下实现功耗的降低。 结果，与现有技术相比，延迟裕度可以降低，这也有助于降低功耗。

公开(公告)号：US20130010559A1

公开(公告)日：2013-01-10

申请号：US13176858

申请日：2011-07-06

申请人： Shih-Huang Huang

发明人： Shih-Huang Huang

IPC分类号： G11C7/12

CPC分类号： G11C7/062 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/12 ,  G11C7/18

摘要： The invention provides a memory output circuit. The memory output circuit is capable of receiving bit line data and bit bar line data output by a memory cell array. In one embodiment, the memory output circuit comprises a pre-charge circuit, a pre-amplifier circuit, and a sense amplifier. The pre-charge circuit is capable of pre-charging a first node and a first inverse node wherein the bit line data and bit bar line data are respectively output to the first node and the first inverse node. The pre-amplifier circuit is capable of generating a second voltage on a second node and a second inverse voltage on a second inverse node according to a first voltage on the first node and a first inverse voltage on the first inverse node. The sense amplifier is capable of detecting the second voltage on the second node and the second inverse voltage on the second inverse node to generate a third voltage on a third node and a third inverse voltage on a third inverse node.

摘要翻译： 本发明提供一种存储器输出电路。 存储器输出电路能够接收由存储单元阵列输出的位线数据和位线数据。 在一个实施例中，存储器输出电路包括预充电电路，前置放大器电路和读出放大器。 预充电电路能够对第一节点和第一逆节点进行预充电，其中位线数据和位线数据被分别输出到第一节点和第一逆节点。 前置放大器电路能够根据第一节点上的第一电压和第一反向节点上的第一反向电压在第二节点上产生第二电压和第二反向节点上的第二反向电压。 感测放大器能够检测第二节点上的第二电压和第二反向节点上的第二反向电压，以在第三节点上产生第三电压，并在第三反向节点上产生第三反向电压。

公开(公告)号：US06813205B2

公开(公告)日：2004-11-02

申请号：US10604508

申请日：2003-07-28

申请人： Shih-Huang Huang

发明人： Shih-Huang Huang

IPC分类号： G11C700

CPC分类号： H01F19/08 ,  G11C7/065 ,  G11C7/12 ,  H01F17/0033

摘要： A pre-charge and sense out circuit for differential type ROM. The ROM is capable of connecting to either a first bit line or a second bit line. The pre-charge and sense out circuit contains a pre-charging module electrically connected to the first and the second bit lines, for pre-charging the first and the second bit lines; a selecting module electrically connected to the first bit line, the second bit line, a first data line, and a second data line, for transmitting data according to a first control signal; a charge sharing module electrically connected to the first and the second data lines, for sharing electrical charges to the first and the second data lines; and a sensing module electrically connected to the first and the second data lines, for sensing signals on the first and the second data lines so as to generate an output signal.

摘要翻译： 差分型ROM的预充电和感应输出电路。 ROM能够连接到第一位线或第二位线。 预充电和感测输出电路包括电连接到第一和第二位线的预充电模块，用于对第一和第二位线进行预充电; 电连接到第一位线，第二位线，第一数据线和第二数据线的选择模块，用于根据第一控制信号发送数据; 电连接到所述第一数据线和所述第二数据线的电荷共享模块，用于向所述第一和第二数据线共享电荷; 以及电连接到第一和第二数据线的感测模块，用于感测第一和第二数据线上的信号，以产生输出信号。