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    Single event upset tolerant memory device
    1.
    发明授权
    Single event upset tolerant memory device 有权

    公开(公告)号：US12045469B2

    公开(公告)日：2024-07-23

    申请号：US18082223

    申请日：2022-12-15

    Applicant: XILINX, INC.

    Inventor： Kumar Rahul ,  John J. Wuu ,  Santosh Yachareni ,  Nui Chong ,  Cheang Whang Chang

    IPC: G06F12/00 ,  G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0673

    Abstract: A memory device is disclosed herein that leverages high ratio column MUXES to improve SEU resistance. The memory device may be utilized in an integrated circuit die and chip packages having the same. In one example, as semiconductor memory device is provided that includes first and second arrays of semiconductor memory cells, a plurality of sense amplifiers configured to read data states from the first and second arrays of memory cells, and a first plurality of high ratio MUXES connecting the first and second arrays of memory cells to the plurality of sense amplifiers.

    IN-DIE TRANSISTOR CHARACTERIZATION IN AN IC
    2.
    发明申请
    IN-DIE TRANSISTOR CHARACTERIZATION IN AN IC 审中-公开
    IC中的In-DIE晶体管特性

    公开(公告)号：US20160097805A1

    公开(公告)日：2016-04-07

    申请号：US14505240

    申请日：2014-10-02

    Applicant: Xilinx, Inc

    Inventor： Ping-Chin Yeh ,  John K. Jennings ,  Rhesa Nathanael ,  Nui Chong ,  Cheang-Whang Chang ,  Daniel Y. Chung

    IPC: G01R31/28

    CPC classification number: G01R31/2851 ,  G01R31/2837 ,  G01R31/2843 ,  G01R31/3167

    Abstract: In an example implementation, an integrated circuit (IC) includes: a plurality of transistors disposed in a plurality of locations on a die of the IC; conductors coupled to terminals of each of the plurality of transistors; a digital-to-analog converter (DAC), coupled to the conductors, to drive voltage signals to the plurality of transistors in response to a digital input; and an analog-to-digital converter (ADC), coupled to at least a portion of the conductors, to generate samples in response to current signals induced in the plurality of transistors in response to the voltage signals, the samples being indicative of at least one electrostatic characteristic for the plurality of transistors.

    Abstract translation: 在示例实现中，集成电路（IC）包括：设置在IC的管芯上的多个位置中的多个晶体管; 耦合到所述多个晶体管中的每一个的端子的导体; 耦合到所述导体的数模转换器（DAC），以响应于数字输入将电压信号驱动到所述多个晶体管; 以及耦合到所述导体的至少一部分的模数转换器（ADC），以响应于所述电压信号而响应于在所述多个晶体管中感应的电流信号而生成样本，所述样本至少指示 一个静电特性用于多个晶体管。

    Test circuits for testing a die stack
    3.
    发明授权
    Test circuits for testing a die stack 有权

    公开(公告)号：US11054461B1

    公开(公告)日：2021-07-06

    申请号：US16351310

    申请日：2019-03-12

    Applicant: Xilinx, Inc.

    Inventor： Nui Chong ,  Amitava Majumdar ,  Cheang-Whang Chang ,  Henley Liu ,  Myongseob Kim ,  Albert Shih-Huai Lin

    IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/3177 ,  H01L25/065

    Abstract: Device(s) and method(s) related generally to a wafer or die stack are disclosed. In one such device, a die stack of two or more integrated circuit dies has associated therewith test circuits corresponding to each level of the die stack each with a set of pads. A test data-input path includes being from: a test data-in pad through a test circuit to a test data-out pad of each of the test circuits; and the test data-out pad to the test data-in pad between consecutive levels of the test circuits. Each of the set of pads includes the test data-in pad and the test data-out pad respectively thereof. A test data-output path is coupled to the test data-out pad of a level of the levels.

    Integrated circuit skew determination
    4.
    发明授权
    Integrated circuit skew determination 有权

    公开(公告)号：US10756711B1

    公开(公告)日：2020-08-25

    申请号：US16682835

    申请日：2019-11-13

    Applicant: XILINX, INC.

    Inventor： Amitava Majumdar ,  Nui Chong

    IPC: H03K3/03 ,  H03K3/017 ,  H03K3/011

    Abstract: Examples described herein provide determining skew of transistors on an integrated circuit. In an example, an integrated circuit includes a ring oscillator and first and second detector circuits. The ring oscillator includes serially connected buffers. Each buffer includes serially connected inverters that include transistors. A transistor of each buffer has a different strength of another transistor of the respective buffer. The first and second detector circuits are connected to different first and second tap nodes, respectively, along the serially connected buffers. The first detector circuit is configured to count a number of cycles of a reference clock that a cyclic signal on the first tap node is either a logically high or low level. The second detector circuit is configured to count a number of cycles of the reference clock that a cyclic signal on the second tap node is either a logically high or low level.

    Chip package assembly with modular core dice
    5.
    发明授权
    Chip package assembly with modular core dice 有权

    公开(公告)号：US10692837B1

    公开(公告)日：2020-06-23

    申请号：US16041530

    申请日：2018-07-20

    Applicant: Xilinx, Inc.

    Inventor： Myongseob Kim ,  Henley Liu ,  Cheang-Whang Chang ,  Nui Chong

    IPC: H01L23/544 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00

    Abstract: A chip package assembly and method for fabricating the same are provided which utilize at least one modular core dice to reduce the cost of manufacture. The modular core dice include at least two die disposed on a wafer segment that are separated by a scribe lane. In one example, a chip package assembly is provided that includes an interconnect substrate stacked below a first wafer segment. The first wafer segment has a first die spaced from a second die by a first scribe lane. The interconnect substrate has conductive routing that is electrically connected to the first die and the second die through die connections.

    Wafer testing and structures for wafer testing
    7.
    发明授权
    Wafer testing and structures for wafer testing 有权

    公开(公告)号：US11650249B1

    公开(公告)日：2023-05-16

    申请号：US16941422

    申请日：2020-07-28

    Applicant: XILINX, INC.

    Inventor： Yan Wang ,  Nui Chong

    IPC: G01R31/3185 ,  G01R31/28 ,  G01R3/00

    CPC classification number: G01R31/318511 ,  G01R31/2884

    Abstract: Examples described herein generally relate to wafer testing and structures implemented on a wafer for wafer testing. In an example method for testing a wafer, power is applied to a first pad in a test site (TS) region on the wafer. The TS region is electrically connected to a device under test (DUT) region on the wafer. The DUT region includes a DUT. The TS region and DUT region are in a first and second scribe line, respectively, on the wafer. A third scribe line is disposed on the wafer between the TS region and the DUT region. A signal is detected from a second pad in the TS region on the wafer. The signal is at least in part a response of the DUT to the power applied to the first pad.

    Testing of bonded wafers and structures for testing bonded wafers
    9.
    发明授权
    Testing of bonded wafers and structures for testing bonded wafers 有权

    公开(公告)号：US11119146B1

    公开(公告)日：2021-09-14

    申请号：US16997630

    申请日：2020-08-19

    Applicant: XILINX, INC.

    Inventor： Nui Chong ,  Yan Wang ,  Hui-Wen Lin

    IPC: G01R31/28 ,  H01L21/66

    Abstract: Examples described herein generally relate to testing of bonded wafers and structures implemented for such testing. In an example method, power is applied to a first pad on a stack of bonded wafers. A wafer of the stack includes a process control monitor (PCM) region that includes structure regions. Each structure region is a device under test region, dummy region, and/or chain interconnect region (CIR). The stack includes a serpentine chain test structure (SCTS) electrically connected between first and second metal features in the wafer in first and second CIRs, respectively, in the PCM region. The SCTS includes segments, one or more of which are disposed between neighboring structure regions in the PCM region that are not the first and second CIRs. A signal is detected from a second pad on the stack. The first and second pads are electrically connected to the first and second metal features, respectively.

    Selectively disconnecting a memory cell from a power supply
    10.
    发明授权
    Selectively disconnecting a memory cell from a power supply 有权

    公开(公告)号：US10566050B1

    公开(公告)日：2020-02-18

    申请号：US15927797

    申请日：2018-03-21

    Applicant: Xilinx, Inc.

    Inventor： Shidong Zhou ,  Nui Chong ,  Jing Jing Chen

    IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412 ,  G11C11/418

    Abstract: Embodiments herein describe a memory cell (e.g., a SRAM memory cell) that includes power selection logic for disconnecting storage inverters from a reference voltage source when writing data into the cell. In one embodiment, the memory cells may be disposed long distances (e.g., more than 100 microns) from the data drivers in the integrated circuit which can result in the data lines having large RC time constants. In one embodiment, disconnecting the memory cells from a power supply may counter (or mitigate) the large RC time constants of the data lines.

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