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公开(公告)号：US07808806B2
公开(公告)日：2010-10-05
申请号：US11984932
申请日：2007-11-26
IPC分类号： G11C5/06
摘要： In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.
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公开(公告)号：US07907434B2
公开(公告)日：2011-03-15
申请号：US11984932
申请日：2007-11-26
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G11C5/00 , G11C5/04 , G11C5/063 , H01L25/0652 , H01L25/0657 , H01L27/105 , H01L2224/48091 , H01L2225/0651 , H01L2225/06513 , H01L2225/06562 , H01L2924/13091 , H04L12/40 , H04L12/4625 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.
摘要翻译： 在本发明的半导体装置中，设置有多个电路部件。 第一条总线将电路组件互连。 第二总线将电路组件互连。 当从一个电路部件发送信号到另一个电路部件时，切换单元输出使每个电路部件选择第一总线和第二总线中的一个的选择信号。 第二个总线的大小大于第一个总线的大小。
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公开(公告)号：US20080142847A1
公开(公告)日：2008-06-19
申请号：US11984932
申请日：2007-11-26
IPC分类号： H01L23/50
CPC分类号： G11C5/06 , G11C5/00 , G11C5/04 , G11C5/063 , H01L25/0652 , H01L25/0657 , H01L27/105 , H01L2224/48091 , H01L2225/0651 , H01L2225/06513 , H01L2225/06562 , H01L2924/13091 , H04L12/40 , H04L12/4625 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.
摘要翻译： 在本发明的半导体装置中，设置有多个电路部件。 第一条总线将电路组件互连。 第二总线将电路组件互连。 当从一个电路部件发送信号到另一个电路部件时，切换单元输出使每个电路部件选择第一总线和第二总线中的一个的选择信号。 第二个总线的大小大于第一个总线的大小。
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公开(公告)号：US06727533B2
公开(公告)日：2004-04-27
申请号：US09956973
申请日：2001-09-21
IPC分类号： H01L31112
CPC分类号： G11C5/06 , G11C5/00 , G11C5/04 , G11C5/063 , H01L25/0652 , H01L25/0657 , H01L27/105 , H01L2224/48091 , H01L2225/0651 , H01L2225/06513 , H01L2225/06562 , H01L2924/13091 , H04L12/40 , H04L12/4625 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.
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公开(公告)号：US07317241B2
公开(公告)日：2008-01-08
申请号：US11143649
申请日：2005-06-03
IPC分类号： H01L23/58
CPC分类号： G11C5/06 , G11C5/00 , G11C5/04 , G11C5/063 , H01L25/0652 , H01L25/0657 , H01L27/105 , H01L2224/48091 , H01L2225/0651 , H01L2225/06513 , H01L2225/06562 , H01L2924/13091 , H04L12/40 , H04L12/4625 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.
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公开(公告)号：US20050218432A1
公开(公告)日：2005-10-06
申请号：US11143649
申请日：2005-06-03
IPC分类号： G11C5/00 , G11C5/06 , H01L25/065 , H01L27/105 , H01L29/80 , H01L31/0336 , H01L31/109 , H01L31/112 , H04L12/46
CPC分类号： G11C5/06 , G11C5/00 , G11C5/04 , G11C5/063 , H01L25/0652 , H01L25/0657 , H01L27/105 , H01L2224/48091 , H01L2225/0651 , H01L2225/06513 , H01L2225/06562 , H01L2924/13091 , H04L12/40 , H04L12/4625 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.
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公开(公告)号：US06185149B2
公开(公告)日：2001-02-06
申请号：US09340147
申请日：1999-06-28
申请人： Shinya Fujioka , Masao Taguchi , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Yasurou Matsuzaki , Toshiya Uchida
发明人： Shinya Fujioka , Masao Taguchi , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Yasurou Matsuzaki , Toshiya Uchida
IPC分类号： G11C800
CPC分类号： G11C7/1018 , G11C7/1072
摘要： A semiconductor memory includes memory cell blocks, a burst-length information generating circuit which generates burst-length information based on a burst length, and a block enable circuit which receives the burst-length information. The block enable circuit selectively enables one of the memory cell blocks when the burst length is equal to or shorter than a predetermined burst length and selectively enables a plurality of memory cell blocks based on the burst length when the burst length is longer than the predetermined burst length. Data are read from the above-mentioned one or plurality of memory cell blocks.
摘要翻译： 半导体存储器包括存储单元块，基于突发长度生成突发长度信息的突发长度信息产生电路，以及接收脉冲串长度信息的块使能电路。 当突发长度等于或小于预定突发长度时，块使能电路选择性地启用存储单元块中的一个，并且当突发长度长于预定突发时，基于脉冲串长度选择性地启用多个存储单元块 长度。 从上述一个或多个存储单元块读取数据。
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8.发明授权公开(公告)号：US06771108B2
公开(公告)日：2004-08-03
申请号：US10152614
申请日：2002-05-23
IPC分类号： H03K300
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/222 , G11C7/225 , G11C7/227 , G11C11/406 , G11C11/40615 , H03L7/0814
摘要： An input circuit has an input buffer and a detection circuit. The input buffer receives an external signal and outputs an internal signal. The detection circuit detects whether or not the external signal is provided. The input buffer outputs the internal signal when an output of the detection circuit indicates that the external signal is provided. This arrangement shortens the lock-on time of an internal circuit (synchronous circuit).
摘要翻译： 输入电路具有输入缓冲器和检测电路。 输入缓冲器接收外部信号并输出内部信号。 检测电路检测外部信号是否被提供。 当检测电路的输出指示提供外部信号时，输入缓冲器输出内部信号。 这种布置缩短了内部电路（同步电路）的锁定时间。
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9.发明授权
公开(公告)号：US6078514A
公开(公告)日：2000-06-20
申请号：US61023
申请日：1998-04-16
申请人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Takaaki Suzuki , Hiroyoshi Tomita , Toshiya Uchida , Yasuharu Sato , Atsushi Hatakeyama , Masato Matsumiya , Yasurou Matsuzaki
发明人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Takaaki Suzuki , Hiroyoshi Tomita , Toshiya Uchida , Yasuharu Sato , Atsushi Hatakeyama , Masato Matsumiya , Yasurou Matsuzaki
IPC分类号： G11C11/41 , G11C7/10 , G11C7/22 , G11C11/401 , H01L21/60 , H01L25/00 , H01L27/10 , H01L25/04 , H01L23/36
CPC分类号： H01L23/60 , G11C7/1006 , G11C7/22 , H01L24/49 , H01L25/0655 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/49175 , H01L24/48 , H01L27/0266 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/1305 , H01L2924/13091 , H01L2924/30105
摘要： A semiconductor system includes at least one logic chip and at least one memory chip arranged such that one side of the at least one memory chip faces one side of the at least one logic chip. The semiconductor system further includes first input/output nodes, provided for the at least one logic chip, for data transfer with an adjacent memory chip, second input/output nodes, provided for the at least one memory chip, for data transfer with an adjacent logic chip, and a package housing the at least one logic chip and the at least one memory chip, wherein the first input/output nodes are arranged along the one side of the at least one logic chip, and the second input/output nodes are arranged along the one side of the at least one memory chip.
摘要翻译： 半导体系统包括至少一个逻辑芯片和布置成使得至少一个存储器芯片的一侧面向至少一个逻辑芯片的一侧的至少一个存储器芯片。 所述半导体系统还包括为所述至少一个逻辑芯片提供的用于与相邻存储器芯片进行数据传输的第一输入/输出节点，为所述至少一个存储器芯片提供的第二输入/输出节点，用于与相邻的 逻辑芯片以及容纳所述至少一个逻辑芯片和所述至少一个存储器芯片的封装，其中所述第一输入/输出节点沿着所述至少一个逻辑芯片的一侧布置，并且所述第二输入/输出节点是 沿着至少一个存储器芯片的一侧布置。
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公开(公告)号：US07120761B2
公开(公告)日：2006-10-10
申请号：US10284092
申请日：2002-10-31
申请人： Yasurou Matsuzaki , Takaaki Suzuki , Masafumi Yamazaki , Kenichi Kawasaki , Shinnosuke Kamata , Ayako Sato , Masato Matsumiya
发明人： Yasurou Matsuzaki , Takaaki Suzuki , Masafumi Yamazaki , Kenichi Kawasaki , Shinnosuke Kamata , Ayako Sato , Masato Matsumiya
IPC分类号： G06F12/00
CPC分类号： G11C8/16 , G06F13/1605 , G11C7/1039 , G11C7/1075 , G11C7/1078 , G11C7/22 , G11C8/18 , G11C11/24 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/409 , G11C11/4093 , G11C2207/107 , G11C2207/108
摘要： A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.
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