公开(公告)号：US09697161B2

公开(公告)日：2017-07-04

申请号：US14219850

申请日：2014-03-19

申请人： STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l.

发明人： Daniele Mangano ,  Ignazio Antonino Urzi

IPC分类号： G06F13/40 ,  G06F13/14 ,  G06F15/78

CPC分类号： G06F13/4027 ,  G06F13/14 ,  G06F15/7825 ,  G06F2213/0038 ,  H04Q2213/13399 ,  H04Q2213/399

摘要： A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.

公开(公告)号：US08592969B2

公开(公告)日：2013-11-26

申请号：US12605169

申请日：2009-10-23

申请人： Bruno Dehos ,  Bruno Lagoguez

发明人： Bruno Dehos ,  Bruno Lagoguez

IPC分类号： H01L23/52

CPC分类号： H01L23/552 ,  H01L23/5389 ,  H01L25/16 ,  H01L2924/1532 ,  H05K1/0218 ,  H05K1/0298 ,  H05K1/141 ,  H05K1/185 ,  H05K3/3436 ,  H05K2201/0723 ,  H05K2201/10674

摘要： A multi-layer substrate has a front face with external pads. An integrated-circuit chip is positioned inside of the multi-layer substrate. An electronic and/or electric component is also positioned inside of the substrate above the integrated-circuit chip. An electrical connection network is formed in the multi-layer substrate to selectively connect the integrated-circuit chip and component together and to the external pads. A first screen is positioned within the multi-layer substrate between the integrated-circuit chip and the electrical connection network, this first screen being connected by vias to the external pads. A second screen is position on a top (external) surface of the multi-layer substrate above the component and electrical connection network, this second screen being connected by vias to the external pads. The integrated-circuit chip is position to be inside the first and second screens.

摘要翻译： 多层基板具有带有外部焊盘的正面。 集成电路芯片位于多层基板的内部。 电子和/或电气部件也位于集成电路芯片上方的衬底的内部。 电连接网络形成在多层基板中，以将集成电路芯片和部件选择性地连接在一起并连接到外部焊盘。 第一屏幕位于集成电路芯片和电连接网络之间的多层基板内，该第一屏幕通过通孔连接到外部焊盘。 第二屏幕位于组件和电连接网络上方的多层基板的顶部（外部）表面上，该第二屏幕通过通孔连接到外部焊盘。 集成电路芯片位于第一和第二屏幕的内部。

公开(公告)号：US08566670B2

公开(公告)日：2013-10-22

申请号：US13192241

申请日：2011-07-27

申请人： Sergio Bacchin ,  Andre Roger ,  Charles Aubenas

发明人： Sergio Bacchin ,  Andre Roger ,  Charles Aubenas

IPC分类号： G11C29/00

CPC分类号： G11C11/412 ,  G06F11/1052 ,  G11C7/1006 ,  G11C11/413 ,  G11C2029/0411

摘要： An SRAM memory device including a plurality of memory cells arranged in a plurality of rows and a plurality of columns; each row of memory cells is adapted to store a RAM word; the RAM word includes a corresponding data word, a corresponding ECC word to be used for error detection and correction purposes and a corresponding applicative word to be used during debugging operations. The SRAM memory device further includes a configurable port adapted to receive a RAM word and to program corresponding memory cells of a selected row based on the received RAM word during a writing access of the SRAM memory device. The SRAM memory device further includes a memory controller unit including circuitry for selectively configuring the configurable port in one among a plurality of modes. The plurality of modes includes a first mode, wherein the configurable port is configured in such a way to disable the programming of the data word and of the corresponding ECC word of the received RAM word and at the same time enable the programming of the applicative word of the received RAM word during the writing access. The plurality of modes includes a second mode, wherein the configurable port is configured in such a way to disable the programming of the applicative word of the received RAM word and at the same time enable the programming of the data word and of the corresponding ECC word of the received RAM word during the writing access.

摘要翻译： 一种SRAM存储器件，包括以多行和多列布置的多个存储单元; 每行存储单元适于存储RAM字; RAM字包括相应的数据字，用于错误检测和校正目的的相应ECC字以及在调试操作期间使用的对应字。 SRAM存储器件还包括可配置端口，其适于在SRAM存储器件的写入访问期间基于所接收的RAM字来接收RAM字并编程所选行的相应存储器单元。 SRAM存储器装置还包括存储器控制器单元，其包括用于在多个模式之一中选择性地配置可配置端口的电路。 多个模式包括第一模式，其中可配置端口被配置为禁止数据字和所接收的RAM字的相应ECC字的编程，并且同时使得应用字的编程 在写入访问期间接收到的RAM字。 多个模式包括第二模式，其中可配置端口被配置为禁止所接收的RAM字的应用字的编程，并且同时使得能够对数据字和对应的ECC字进行编程 在写入访问期间接收到的RAM字。

公开(公告)号：US08541791B2

公开(公告)日：2013-09-24

申请号：US12968507

申请日：2010-12-15

申请人： Roch Espiau de Lamaestre ,  Jean-Jacques Greffet ,  Bernard Guillaumot ,  Ruben Esteban Llorente

发明人： Roch Espiau de Lamaestre ,  Jean-Jacques Greffet ,  Bernard Guillaumot ,  Ruben Esteban Llorente

IPC分类号： H01L27/15

CPC分类号： H01L33/0041 ,  H01L33/06 ,  H01L33/405 ,  H01L33/465

摘要： A source of photons resulting from a recombination of localized excitons, including a semiconductor layer having a central portion surrounded with heavily-doped regions; above said central portion, a layer portion containing elements capable of being activated by excitons, coated with a first metallization; and under the semiconductor layer, a second metallization of greater extension than the first metallization. The distance between the first and second metallizations is on the order of from 10 to 60 nm; and the lateral extension of the first metallization is on the order of from λ0/10*ne to λ0/2*ne, where λ0 is the wavelength in vacuum of the emitted light and ne is the effective refractive index of the mode formed in the cavity created by the two metallizations.

摘要翻译： 由局部激子的复合产生的光子源，包括具有被重掺杂区域包围的中心部分的半导体层; 在所述中心部分上方，包含能够被激子激活的元件的层部分，涂覆有第一金属化; 并且在所述半导体层下方具有比所述第一金属化更大延伸的第二金属化。 第一和第二金属化之间的距离为10至60nm; 并且第一金属化的横向延伸为从λ0/ 10 * ne到λ0/ 2 * ne的数量级，其中λ0是发射光的真空中的波长，ne是在发射光中形成的模式的有效折射率 由两个金属化产生的腔。

公开(公告)号：US08285236B2

公开(公告)日：2012-10-09

申请号：US12505671

申请日：2009-07-20

申请人： Antoine Hue ,  Gabriel Della-Monica ,  Florent Sibille

发明人： Antoine Hue ,  Gabriel Della-Monica ,  Florent Sibille

IPC分类号： H04B17/00 ,  H04B1/00 ,  H04L27/08

CPC分类号： H04L25/063

摘要： A method may compensate for direct current (DC) offset in a radio frequency reception device. The method may include partitioning an analog portion of the reception device into a plurality of zones, for each zone, calibrating initial DC offset compensation to be applied within an operating range of a respective zone, the operating range of the other zones being limited to a threshold operating range, and determining DC offset compensation to be applied to the reception device throughout the operating range based on the basic DC offset compensations.

摘要翻译： 一种方法可以补偿射频接收装置中的直流（DC）偏移。 该方法可以包括将接收设备的模拟部分划分成多个区域，对于每个区域，校准要在相应区域的操作范围内施加的初始DC偏移补偿，其它区域的操作范围被限制为 阈值操作范围，以及基于所述基本DC偏移补偿，确定在所述操作范围内对所述接收装置施加的DC偏移补偿。

公开(公告)号：US08283968B2

公开(公告)日：2012-10-09

申请号：US12712027

申请日：2010-02-24

申请人： Serge Ramet

发明人： Serge Ramet

IPC分类号： H03K17/16 ,  H03K17/687

CPC分类号： H03K17/145 ,  H03K17/063 ,  H03K17/687 ,  H03K2217/0018

摘要： An analog switch including at least one first MOS transistor capable of transferring a signal from a first terminal to a second terminal; a connection circuit for bringing a substrate terminal of the first transistor to a voltage which is a function of the voltages of the first and second terminals; and a circuit for controlling a control voltage of the first transistor with the signal.

摘要翻译： 一种模拟开关，包括能够将信号从第一端子传送到第二端子的至少一个第一MOS晶体管; 连接电路，用于将第一晶体管的衬底端子与第一和第二端子的电压成为一个电压; 以及用于利用所述信号来控制所述第一晶体管的控制电压的电路。

公开(公告)号：US08165120B2

公开(公告)日：2012-04-24

申请号：US12291460

申请日：2008-11-10

申请人： Giuseppe Maruccia ,  Riccardo Locatelli ,  Lorenzo Pieralisi ,  Marcello Coppola

发明人： Giuseppe Maruccia ,  Riccardo Locatelli ,  Lorenzo Pieralisi ,  Marcello Coppola

IPC分类号： H04L12/56

CPC分类号： H04L49/9063 ,  H04L49/3063 ,  H04L49/3072 ,  H04L49/90 ,  H04L49/9042

摘要： This method for transferring data through a network on chip (NoC) between a first electronic device and a second electronic device, comprising: retrieving from the first device request packets comprising request control data for controlling data transfer and actual request data to be transferred; storing said request control and data to be transferred in memory means provided in an network interface (NI); and elaborating data packets to be transferred to the second device through said network, said data packets comprising a header and a payload elaborated from said control data and said actual data, respectively; The control data and the actual data to be transferred are stored in separate first and second memory means.

摘要翻译： 该方法用于通过芯片上的网络（NoC）在第一电子设备和第二电子设备之间传送数据，包括：从第一设备检索请求包括用于控制数据传送的请求控制数据和要传送的实际请求数据的分组; 将所述请求控制和要传送的数据存储在网络接口（NI）中提供的存储装置中; 并且通过所述网络详细描述要传送到第二设备的数据分组，所述数据分组包括分别从所述控制数据和所述实际数据详细描述的报头和有效载荷; 要传送的控制数据和实际数据被存储在单独的第一和第二存储装置中。

公开(公告)号：US20100290646A1

公开(公告)日：2010-11-18

申请号：US12781552

申请日：2010-05-17

申请人： Gaël Pillonnet ,  Remy Cellier

发明人： Gaël Pillonnet ,  Remy Cellier

IPC分类号： H03F99/00 ,  H03F3/217

CPC分类号： H03F3/2171

摘要： An amplifier having at least one switch controlled by an output voltage of a hysteresis block, wherein the hysteresis block is adapted to receive an input voltage signal based on an integration of an error signal, a low threshold voltage and a high threshold voltage, and is arranged to change the output voltage from a first value to a second value when the input voltage signal is higher than the high threshold voltage and to change the output voltage from the second value to the first value when the input voltage signal is lower than the low threshold voltage, and wherein the low threshold voltage is equal to Vref−αVDD and the high threshold voltage is equal to Vref+αVDD, where Vref is a common mode voltage level, α is a non-zero constant, and VDD is a power supply voltage.

摘要翻译： 具有至少一个由滞后块的输出电压控制的开关的放大器，其中所述滞后块适于基于误差信号，低阈值电压和高阈值电压的积分来接收输入电压信号，并且是 布置成当输入电压信号高于高阈值电压时将输出电压从第一值改变为第二值，并且当输入电压信号低于低电平时，将输出电压从第二值改变为第一值 阈值电压，并且其中低阈值电压等于Vref-αVDD，并且高阈值电压等于Vref +αVDD，其中Vref是共模电压电平，α是非零常数，VDD是电源 电压。

公开(公告)号：US20100039180A1

公开(公告)日：2010-02-18

申请号：US12539644

申请日：2009-08-12

申请人： Serge Pontarollo ,  Serge Ramet

发明人： Serge Pontarollo ,  Serge Ramet

IPC分类号： H03F3/16

CPC分类号： H03F3/3027 ,  H03F1/0261 ,  H03F1/308 ,  H03F1/3205 ,  H03F1/3217 ,  H03F1/342 ,  H03F2200/135 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/513

摘要： An amplifier having an output stage with a complementary pair of first and second transistors each coupled to an output node of the amplifier; control circuitry arranged to provide a control signal at a control node of the first transistor based on the voltage at an input node of the amplifier; and adjustment circuitry arranged to adjust the control signal to maintain the current through the first transistor above a minimum value.

摘要翻译： 一种具有输出级的放大器，其具有互补的一对第一和第二晶体管，每个耦合到放大器的输出节点; 控制电路被布置成基于放大器的输入节点处的电压在第一晶体管的控制节点处提供控制信号; 以及调整电路，其布置成调整所述控制信号以将通过所述第一晶体管的电流保持在最小值以上。

公开(公告)号：US20090257651A1

公开(公告)日：2009-10-15

申请号：US12417546

申请日：2009-04-02

申请人： Gilles Ries ,  Tan Sun

发明人： Gilles Ries ,  Tan Sun

IPC分类号： G06K9/36

CPC分类号： G09G5/04 ,  G09G2340/02 ,  G09G2370/16 ,  H04N19/105 ,  H04N19/176 ,  H04N19/182 ,  H04N19/184 ,  H04N19/186 ,  H04N19/90 ,  H04N19/91

摘要： A method of compressing at least a part of a digital image comprises the steps of: dividing said digital image into groups of pixels; assigning a first information to each group of pixels wherein said first information indicates at least two reference colors selected for said group of pixels and, for each pixel in said group of pixels, which reference color or combination thereof is selected; assigning a second information to each group of pixels indicating a mode of compression used for said group of pixels; said first information indicating at least a third color for at least one of said groups of pixels.

摘要翻译： 压缩数字图像的至少一部分的方法包括以下步骤：将所述数字图像分割成像素组; 将第一信息分配给每个像素组，其中所述第一信息指示为所述像素组选择的至少两个参考颜色，并且对于所述像素组中的每个像素，选择哪个参考颜色或其组合; 向指示用于所述像素组的压缩模式的每个像素组分配第二信息; 所述第一信息指示至少一个所述像素组中的一个的至少第三颜色。