公开(公告)号：US12119373B2

公开(公告)日：2024-10-15

申请号：US18080976

申请日：2022-12-14

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Jeffrey Alan West

IPC分类号： H01L21/02 ,  H01L49/02

CPC分类号： H01L28/60 ,  H01L28/56

摘要： A method forms a first voltage node of a high voltage component of a microelectronic device. The method also forms a plurality of dielectric layers. The method also forms a second voltage node of the high voltage component of the microelectronic device in a fourth position such that the plurality of dielectric layers is between the first voltage node and the second voltage node. During the forming a second voltage node step, a portion of a third layer in the plurality of dielectric layers, in a region outwardly positioned relative to the second voltage node, is removed to expose the second layer, in the plurality of dielectric layers, in the region.

公开(公告)号：US12057471B2

公开(公告)日：2024-08-06

申请号：US18354573

申请日：2023-07-18

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Han-Jong Chia ,  Mauricio Manfrini

IPC分类号： H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L49/02 ,  H10B51/30 ,  H10B53/30

CPC分类号： H01L28/56 ,  H01L21/02601 ,  H01L28/60 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/78696 ,  H10B51/30 ,  H10B53/30

摘要： A memory device, transistor, and methods of making the same, the memory device including a memory cell including: a bottom electrode layer; a high-k dielectric layer disposed on the bottom electrode layer; a discontinuous seed structure comprising discrete particles of a metal disposed on the high-k dielectric layer; a ferroelectric (FE) layer disposed on the seed structure and directly contacting portions of high-k dielectric layer exposed through the seed structure; and a top electrode layer disposed on the FE layer.

公开(公告)号：US12046550B2

公开(公告)日：2024-07-23

申请号：US18109108

申请日：2023-02-13

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Paul Yang ,  Tsun-Kai Tsao ,  Sheng-Chau Chen ,  Sheng-Chan Li ,  Cheng-Yuan Tsai

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L49/02

CPC分类号： H01L23/5223 ,  H01L21/76831 ,  H01L21/76879 ,  H01L23/53266 ,  H01L28/56

摘要： Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.

公开(公告)号：US11980023B2

公开(公告)日：2024-05-07

申请号：US18331493

申请日：2023-06-08

申请人： Samsung Electronics Co., Ltd.

发明人： Jaeho Lee ,  Boeun Park ,  Yongsung Kim ,  Jooho Lee

IPC分类号： G11C11/22 ,  G01G7/00 ,  G01G7/06 ,  G11C19/00 ,  G11C19/18 ,  H01L29/51 ,  H01L49/02 ,  H10B12/00

CPC分类号： H10B12/37 ,  G01G7/00 ,  G01G7/06 ,  G11C11/221 ,  G11C11/223 ,  G11C11/2275 ,  G11C19/005 ,  G11C19/18 ,  H01L28/56 ,  H01L29/516 ,  H10B12/33

摘要： A capacitor comprises a first electrode, a second electrode provided on the first electrode, a ferroelectric film provided between the first electrode and the second electrode, and a dielectric film provided between the ferroelectric film and the second electrode, impedance of the ferroelectric film and impedance of the dielectric film are determined such that a control voltage applied between the first electrode and the second electrode is equal to a capacitance boosting operating voltage, and the capacitance boosting operating voltage is determined by the following equation:





V
MAX

=


(

1
+



❘
"\[LeftBracketingBar]"


Z
2


❘
"\[RightBracketingBar]"




❘
"\[LeftBracketingBar]"


Z
1


❘
"\[RightBracketingBar]"




)

⁢

t
F

⁢

E
FM






where VMAX is a capacitance boosting operating voltage, Z1 is impedance of the ferroelectric film, Z2 is impedance of the dielectric film, tF is a thickness of the ferroelectric film, and EFM is an electric field applied to the ferroelectric film having a maximum polarization.

公开(公告)号：US11949018B2

公开(公告)日：2024-04-02

申请号：US18068438

申请日：2022-12-19

申请人： Kepler Computing Inc.

发明人： Ramesh Ramamoorthy ,  Sasikanth Manipatruni ,  Gaurav Thareja

IPC分类号： H01L21/00 ,  H01L29/20 ,  H01L29/66 ,  H01L29/737 ,  H01L29/74 ,  H01L29/786 ,  H01L49/02 ,  H10B53/30 ,  H10B12/00

CPC分类号： H01L29/78618 ,  H01L28/56 ,  H01L28/57 ,  H01L28/60 ,  H01L28/65 ,  H01L29/2003 ,  H01L29/6684 ,  H01L29/7375 ,  H01L29/7408 ,  H01L29/7869 ,  H10B53/30 ,  H10B12/312 ,  H10B12/36

摘要： The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer

公开(公告)号：US11908943B2

公开(公告)日：2024-02-20

申请号：US18181426

申请日：2023-03-09

申请人： Kepler Computing Inc.

发明人： Ramesh Ramamoorthy ,  Sasikanth Manipatruni ,  Gaurav Thareja

IPC分类号： H01L21/00 ,  H01L29/786 ,  H01L29/66 ,  H01L29/20 ,  H01L29/74 ,  H01L29/737 ,  H01L49/02 ,  H10B53/30 ,  H10B12/00

CPC分类号： H01L29/78618 ,  H01L28/56 ,  H01L28/57 ,  H01L28/60 ,  H01L28/65 ,  H01L29/2003 ,  H01L29/6684 ,  H01L29/7375 ,  H01L29/7408 ,  H01L29/7869 ,  H10B53/30 ,  H10B12/312 ,  H10B12/36

摘要： The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

公开(公告)号：US11855230B2

公开(公告)日：2023-12-26

申请号：US17395779

申请日：2021-08-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chi-Han Yang ,  Lung-Hui Chen ,  Kuan-Yu Chen ,  Shih J. Wei

IPC分类号： H01L29/94 ,  H01L23/522 ,  H01L49/02

CPC分类号： H01L29/94 ,  H01L23/5223 ,  H01L23/5226 ,  H01L28/56 ,  H01L28/91 ,  H01L28/92

摘要： A metallization structure of an integrated circuit (IC) includes: an intermetal dielectric (IMD) layer; a patterned metal layer embedded in the IMD layer; a patterned top metal layer disposed on the IMD layer; electrical vias comprising via material passing through the IMD layer and connecting the patterned top metal layer and the patterned metal layer embedded in the IMD layer; and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes: a first capacitor metal layer comprising the via material contacting an MIM capacitor landing area of the patterned metal layer embedded in the IMD layer; a second capacitor metal layer comprising the via material contacting a first MIM capacitor terminal area of the patterned top metal layer; and an insulator layer disposed between the first capacitor metal layer and the second capacitor metal layer.

公开(公告)号：US11848386B2

公开(公告)日：2023-12-19

申请号：US18181525

申请日：2023-03-09

申请人： Kepler Computing Inc.

发明人： Ramesh Ramamoorthy ,  Sasikanth Manipatruni ,  Gaurav Thareja

IPC分类号： H01L21/00 ,  H01L29/786 ,  H01L29/66 ,  H01L29/20 ,  H01L29/74 ,  H01L29/737 ,  H01L49/02 ,  H10B53/30 ,  H10B12/00

CPC分类号： H01L29/78618 ,  H01L28/56 ,  H01L28/57 ,  H01L28/60 ,  H01L28/65 ,  H01L29/2003 ,  H01L29/6684 ,  H01L29/7375 ,  H01L29/7408 ,  H01L29/7869 ,  H10B53/30 ,  H10B12/312 ,  H10B12/36

摘要： The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

公开(公告)号：US11837664B2

公开(公告)日：2023-12-05

申请号：US18045415

申请日：2022-10-10

申请人： Kepler Computing Inc.

发明人： Ramesh Ramamoorthy ,  Sasikanth Manipatruni ,  Gaurav Thareja

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L29/20 ,  H01L29/74 ,  H01L29/737 ,  H10B53/30 ,  H10B12/00 ,  H01L49/02

CPC分类号： H01L29/78618 ,  H01L28/56 ,  H01L28/57 ,  H01L28/60 ,  H01L28/65 ,  H01L29/2003 ,  H01L29/6684 ,  H01L29/7375 ,  H01L29/7408 ,  H01L29/7869 ,  H10B53/30 ,  H10B12/312 ,  H10B12/36

摘要： The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor, which in turn comprises a polar layer comprising a crystalline base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen, wherein the dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor additionally comprises first and second crystalline conductive or semiconductive oxide electrodes on opposing sides of the polar layer, wherein the polar layer has a lattice constant that is matched within about 20% of a lattice constant of one or both of the first and second crystalline conductive or semiconductive oxide electrodes. The first crystalline conductive or semiconductive oxide electrode serves as a template for growing the polar layer thereon, such that at least a portion of the polar layer is pseudomorphically formed on the first crystalline conductive or semiconductive oxide electrode.

公开(公告)号：US11799029B2

公开(公告)日：2023-10-24

申请号：US17551899

申请日：2021-12-15

申请人： Intel Corporation

发明人： Uygar E. Avci ,  Joshua M. Howard ,  Seiyon Kim ,  Ian A. Young

IPC分类号： H01L29/78 ,  H01L29/51 ,  H10B51/30 ,  H10B53/30 ,  H01L49/02

CPC分类号： H01L29/78391 ,  H01L28/56 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/785 ,  H10B51/30 ,  H10B53/30

摘要： Described is an apparatus which comprises: a first layer comprising a semiconductor; a second layer comprising an insulating material, the second layer adjacent to the first layer; a third layer comprising a high-k insulating material, the third layer adjacent to the second layer; a fourth layer comprising a ferroelectric material, the fourth layer adjacent to the third layer; and a fifth layer comprising a high-k insulating material, the fifth layer adjacent to the fourth layer.